Expansion module including programmable chip selects

ABSTRACT

The present invention relates to a computer system and more particularly to a computer system which allows option controller cards for various input/output (I/O) devices to be added on the motherboard at minimum cost.

This is a continuation of prior application Ser. No. 08/484,446, filedJun. 7, 1995, now U.S. Pat. No. 5,784,642, which is a divisional of Ser.No. 08/043,193, filed Apr. 5, 1993, now abandoned, which is herebyincorporated herein by reference in its entirety.

CROSS REFERENCE TO RELATED APPLICATIONS

This invention is related to the following patent applications: MethodOf Securing Various Functions On An I/O Controller Chip, attorney docketnumber 53552; Method of Remapping Interrupts and DMAs, attorney docketnumber 53553; Method For Providing A Programmable Data Write Hold Time,attorney docket number 53554; and Method For Reading Data From A WriteOnly I/O Port, attorney docket 53555, all filed on even date herewithand subject to an obligation of assignment to Zenith Data SystemsCorporation.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a computer system and more particularlyto a computer system which allows option controller cards for variousinput/output (I/O) devices to be added on the motherboard at minimumcost.

2. Description of the Prior Art

The modern microcomputer must be capable of supporting a wide audienceof users from the hobbyist to the corporate power-user. This requiresthat the computer must support a wide array of peripherals which mightinclude LANs, modems, disk controllers, video controllers, or multimediacontrollers. If the general purpose microcomputer is to address thislarge audience economically, it must provide these functions as optionsto a minimally configured basic machine.

One solution to this problem is to provide multiple industry standardbus slots such as ISA, EISA, MCA, or NuBUS, which the user can use toinstall a third party peripheral controller. The addition of these slotsrequires the system cabinet to be large and bulky. The power supply mustalso be capable of supplying the worst case power required for eachslot, multiplied by the number of slots available.

With the current level of integration available today these peripheralfunctions can often be provided using a single LSI device along withseveral small support devices used for address decoding, resourcerouting, data buffering and interfacing. This amount of circuitry caneasily fit on the smallest, industry standard, bus card and still haveroom to spare. However, regardless of the minimum physical size of thelogic required to implement the function, the user must sacrifice one ofthe, typically few, standard bus slots designed into the computer. Sincethe manufacturer of the computer had to provide enough space and powerto support the worst case (largest) card that could have been installedinto the standard slot, the user ends up paying more than was needed forthe extra capability that has not been used.

SUMMARY OF THE INVENTION

It is an object of the invention to solve various problems in the priorart.

Briefly, the present invention relates to a computer system which allowsa plurality of option controller cards to be added to the motherboard atminimum cost and without the overhead of using bus expansion slots.Various support services, such as address decoding, are provided by themotherboard in order to reduce the size of the option controller cards.

BRIEF DESCRIPTION OF THE DRAWING

These and other objects and advantages of the present invention willbecome readily apparent upon consideration of the following detaileddescription and attached drawing, wherein:

FIG. 1 is a block diagram of the computer system;

FIG. 2 is a schematic diagram of the register file logic illustrated inFIG. 1;

FIG. 3 is a block diagram of the programmable select logic illustratedin FIG. 1;

FIG. 4 is a schematic diagram of the address match logic illustrated inFIG. 3;

FIG. 5 is a schematic diagram of the command match logic illustrated inFIG. 3;

FIG. 6 is a schematic diagram of the index match logic illustrated inFIG. 3;

FIG. 7 is a block/schematic diagram of the direct memory access (DMA)switch register and related circuitry for remapping DMA I/O controllines;

FIG. 8A is a schematic diagram of the demultiplexing logic circuitryused for DMA switching;

FIG. 8B is a truth table corresponding to the logic circuitry of FIG.8A;

FIG. 9A is a schematic diagram of the multiplexing logic circuitry usedfor DMA switching;

FIG. 9B is a truth table corresponding to the logic circuitry of FIG.9A;

FIG. 10 is a schematic diagram of XBUS control logic;

FIG. 11A is a block/schematic diagram of the interrupt request (IRQ)switch register and related circuitry for remapping IRQ I/O controllines;

FIG. 11B is a schematic diagram of the mapping of IRQ inputs to the IRQoutputs;

FIG. 12A is a schematic diagram of the demultiplexing logic circuitryused for IRQ switching;

FIG. 12B is a truth table corresponding to the logic circuitry of FIG.12A;

FIGS. 13A and 13B are programmable DMA and IRQ mapping table is forrecording system I/O configurations;

FIG. 14 is a schematic diagram of the secure-interrupt logic;

FIG. 15 is a schematic diagram of the secure-IOSELECT logic;

FIG. 16 is a schematic diagram of the secure data write logic, and

FIG. 17 is a timing diagram for the XBUS control logic.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A computer system is illustrated in FIG. 1 which includes a systemcontroller 1, a programmable device 2, a system data and address bus 3,an option data bus (XDATA), and an input/output (I/O) option orexpansion card 13 for supporting a plurality of I/O devices. Two I/Odevices, identified with the reference numerals 11 and 12, areillustrated for simplicity. The I/O expansion card 13 is adapted to beplugged into an edge connector (not shown) on the motherboard; thusconserving AT bus expansion slots. The programmable device 2 providesfor the necessary selection, decoding, and resource routing functions tosupport the I/O devices 11 and 12.

As shown, the expansion card 13 is connected to the option data (XDATA)bus, which, in turn, is connected to the system bus 3 by way of a datatransceiver 5. However, it is also contemplated that the expansion card13 can be directly connected to the system data bus 3. Addressing of theI/O devices 11 and 12 is provided by the programmable device 2 as willbe discussed in more detail below.

Bus Description

Various architectures for the system bus 3 are contemplated. Forexample, the system bus 3 can be an industry standard architecture (ISA)bus, an extended industry standard architecture (EISA) bus, amicrochannel architecture (MCA) bus; a video local (VLBUS) bus, or aperipheral component interconnect (PCIBUS) bus.

The option bus is a multiple bit parallel bus, connected to the systembus 3 by way of a data transceiver 5. The data transceiver 5 allows fordata transfers between the system bus 3 and the I/O devices 11 and 12,and between the system data bus 3 and the programmable device 2.

The data transceiver 5 includes a read tri-state device 13 and a writetri-state device 14. These tri-state devices 13 and 14 are enabled bythe read signal XREAD₋₋ EN# and write signal XWRITE₋₋ EN# from theprogrammable device 2, as will be discussed in more detail below.

System Controller

The system controller 1, under the direction of the central processingunit (not shown, CPU), initiates commands on the system bus 3 totransfer data to and from all system peripherals including the I/Odevices 11 and 12. These commands include commands to transfer data froman I/O devices 11, 12 to the system controller 1 and ultimately to theCPU, as well as WRITE commands to transfer data to the I/O devices 11,12 from the system controller 1 and the CPU. The system controller 1also asserts addressing information to the I/O devices 11, 12 toindicate which I/O device 11, 12 is to respond to the command. Theaddressing information is decoded by the programmable device 2, as willbe discussed in more detail below.

Interrupt request lines IRQ allow the I/O devices 11 and 12 toasynchronously notify the system controller 1 when the I/O devices 11and 12 require service. These interrupt request lines IRQ areprioritized and require coordination between the I/O devices 11 and 12and the system software to allow the I/O device's 11, 12 interruptpriority level to be changed during installation and to allow the I/Odevices to coexist with other similar devices. In known systems, themethod of changing the interrupt level is accomplished manually by wayof a jumper or shunt; requiring a certain amount of disassembly of thecomputer system. As will be discussed in more detail below, theinterrupt system described herein is programmable.

The system controller 1 also provides to the system bus 3 a number ofcontrol signals intended to allow the I/O devices 11 and 12 to request adirect memory access (DMA) by way of DMA request signal DRQ. When a DMArequest is received by the system controller 1, it will respond to theI/O devices 11, 12 with a DMA acknowledged signal DACK, assuming thatsystem resources are available. These signals DRQ and DACK are pairedtogether to form a DMA channel. Multiple DMA channels are typicallyprovided in a computer system and are generally allowed to be reroutedfrom one device to another when the need arises. In known systems,rerouting of DMA channels is similar to remapping of an interruptrequest and require the manual changing of various shunts or jumper. Asdescribed below, DMA channel rerouting described herein does not requireany disassembly and is accomplished by software commands.

The system controller 1 does not form a part of the present inventionand includes DMA and IRQ functions as discussed above, as well as buscontrol functions. This system controller 1 may be formed from a singlechip or multiple chips. For example, the DMA and IRQ functions can beprovided on a single chip, such as an Intel model number 82357, whilethe bus control functions may be provided by another chip such as anIntel model 82358.

The Programmable Device

The programmable device 2 provides the necessary selection, decoding,and resource rerouting function necessary to support various I/O devices11 and 12 on the option card 13, as well as the motherboard itself. Inparticular, the programmable device 2 may be used to provide all addressdecoding functions, IRQ, and DMA mapping function for the entiremotherboard.

The programmable device includes register file logic 6, a programmableselect logic 7, option bus control logic 8, interrupt mapping logic 9,and DMA request/acknowledge mapping logic 10.

The programmable device 2 may be implemented as an application specificintegrated circuit (ASIC). The Verilog source code for the ASIC isattached as Appendix 1.

Register File Logic

The register file logic 6 is illustrated in FIG. 2. The register file 6includes all of the programmable storage elements used to configure theprogrammable device 2 along with the decode logic to identify accessesto the programmable device 2. As shown, a plurality of internalregisters 104 through 114 are shown. These internal registers 104through 114 are accessed by the system controller 1 by way of an indexport 91 and a data port 92. In particular, the index port and the dataport can be set at any values, for example, $E0 and $E4. Thus, anytimethe system controller 1 writes the address $E0, the index port decodelogic 91 will assert the INDEX₋₋ WRITE signal when the address matchesthe index port decode address ($E0) during a WRITE operation. TheINDEX₋₋ WRITE signal is utilized by the XBUS control logic 8 (FIG. 1) tocause a XWRITE₋₋ EN# signal to be asserted to enable the datatransceiver 5 to pass system data through to the XDATA bus. The INDEX₋₋WRITE signal also enables an 8-bit index register 90. The index register90 is used to select one of the internal registers 104 through 114 as atarget register for programming. Thus, once the signals XWRITE₋₋ ENABLEand INDEX₋₋ WRITE are asserted, a data byte from the system controller 1is written to the index register and latched as the signals XWRITE₋₋ENABLE and INDEX₋₋ WRITE are deasserted. The output of the indexregister 90 is applied to a register select logic block 93, implementedas a demultiplexer, which selects or enables one of the internalregisters 104 through 114.

When the system controller 1 asserts the address of the data port (e.g.,$E4) and asserts a WRITE command signal, the data port decode logic 92asserts a DATA₋₋ WRITE signal. The DATA₋₋ WRITE signal is used in theXBUS control logic 8 to assert an XWRITE₋₋ EN# signal and to allowsystem data to be connected to the XDATA bus. The assertion of theDATA₋₋ WRITE signal at the register select logic 93 asserts one of theWRITE lines 115 to 125 of the internal registers 104 through 114 whichcorresponds to the target register, thereby loading the data into thatregister.

The accesses to the data port may be qualified for various reasons,including security. In particular, in order to prevent unauthorizedaccess of the data port, accesses to this port 92 may be qualified witha SECURE signal or other signals. As shown in FIG. 1, the SECURE signalmay be from a key switch A to prevent unauthorized modification of theprogrammable device 2.

Each of the registers 104 to 114 in the register file logic 6 can beread back by the system controller 1 (FIG. 1). In particular, all eightbits of each of the registers 104 to 114 are connected to a multiplexer130. When the system controller 1 asserts the data port address (e.g.,$E4), and additionally asserts a READ command, the data port decodelogic 92 will assert a DATA₋₋ READ signal. The data read signal DATA₋₋READ along with bit 7 from the index register 90 are used to control atri-state device 129 to enable the multiplexer 130 output to be appliedto the XDATA bus. In particular, the DATA₋₋ READ signal is applied to anoninverting input of the AND gate 133 while bit 7 of the index register90 is applied to an inverting input of the AND gate 133. The output ofthe AND gate 133 is applied to a tri-state device 129, which, in turn,when enabled, applies the outputs of the selected register 104 to 114 tothe XDATA bus. During this condition, the XREAD₋₋ EN# signal will beenabled from the XBUS control circuit 8 to allow the XDATA bus to beconnected to the system bus 3, which, in turn, allows the output of theregisters 104 to 114 to be read back by the system controller 1.

Bit 7 of the latch 90 may be used to defeat the read back function bythe system controller 1. In particular, if bit 7 is set, then gate 133will be disabled, which, in turn, will disable the tri-state device 129to prevent the data at the output of the registers 104 to 114 from beingread back by the system controller 1.

A data decode signal DATA₋₋ DEC is asserted any time the data portdecode logic 92 indicates that the data port was addressed by the systemcontroller 1. This data decode signal, available at the output on an ORgate 130, is under the control of the DATA₋₋ WRITE and DATA₋₋ READsignals, applied to the inputs of the OR gate 130. This data decodesignal DATA₋₋ DEC is used in other parts of the control logic, includingan index match INDX₋₋ MTCH logic control circuit 162 on FIG. 3 of thedrawings.

Programmable Select Logic

As mentioned above, the programmable device 2 is accessed by way of theregister file logic 6 which includes the internal registers 104 through114. The internal registers 104 through 107 are used to control each ofthe IOSEL0# output signals from the programmable select logic 7, used toselect an I/O device 11, 12 on the expansion card 13. As discussedbelow, the registers 108 through 114 are utilized for DMA and IRQmapping.

The registers 104 through 107 define the ADDRESS and other qualifyingparameters for each output select signal IOSEL. For simplicity, only asingle programmable address output signal IOSEL is described.

The registers 104 through 107 represent the command register CMD₋₋REG[7:0]; the upper address register UADD₋₋ REG[7:0]; the lower addressregister LADD₋₋ REG[7:0]; and the mask register MASK₋₋ REG[7:0].

The command register CMD₋₋ REG[7:0] is used to specify the commands forenabling the I/O select output signal IOSEL and global outputs. Thecommand register CMD₋₋ REG[7:0] is an 8-bit register. Bit 0, when set,allows the signal I/O 16 to be asserted when the programmable outputselect signals IOSEL is asserted. The I/O 16 signal is used to indicateto the system bus 3 that the particular I/O device 11, 12 is capable of16-bit data transfers. Bit 1 is used to qualify the output select signalIOSEL with a PRIVY signal, for example, which may be used to controlaccess to a particular I/O device, such as a hard disk drive (notshown). In particular, as will be discussed in more detail below, whenbit 1 is asserted, the programmable output select signal IOSEL will beenabled. Similarly, when bit 1 is disabled, the output select signalIOSEL will be deasserted unless the programmable select logic 7 is inthe sticky mode, in which case bit 1 is ignored. Bits 4, 3 are used toqualify the programmable output select signal IOSEL with either an I/OWRITE signal IOW or an I/O READ signal IOR. In particular, when bits 4,3equal 0,0, neither the I/O READ signal IOR nor the I/O WRITE signal IOWaffect the I/O select signal IOSEL. When bits 4,3 equal 0,1, the I/OREAD signal IOR is used to qualify or enable the I/O select signalIOSEL. When bits 4,3 equal 1,0, the I/O WRITE signal IOW enables the I/Oselect signal IOSEL. When bits 4,3 equal 1,1, either the I/O READ signalIOR or the I/O WRITE signal IOW can enable the I/O select signal IOSEL.Bits 5,6 are reserved. Bit 7, identified as INDXD, controls the mode ofoperation of the programmable select logic 7. In particular, when bit 7is set, the programmable select logic 7 will be in either the index modeor the sticky mode, depending on whether the sticky bit in the maskregister is set.

When the programmable select logic 7 is in an address decode mode ofoperation, the upper address register UADD₋₋ REG and the lower addressregister LADD₋₋ REG are used to define the upper and lower bytes of theprogrammed address range for the I/O devices 11 and 12 on the expansioncard 13. Both the upper address register UADD₋₋ REG and the loweraddress register LADD₋₋ REG are 8-bit registers.

The mask register MASK₋₋ REG[7:0] is an 8-bit register which allows arange of addresses to be decoded instead of a single address. Each bitin the mask register MASK₋₋ REG[7:0] corresponds to a bit in the loweraddress register LADD₋₋ REG[7:0]. Bit 0 of the mask register MASK₋₋REG[7:0] is used to set the "sticky bit" which enables a sticky mode ofoperation, as will be discussed below.

The programmable select logic 7 (FIG. 3) is adapted to operate in anaddress decode mode, an index decode mode, and a sticky mode. The modeof operation of the programmable select logic 7 is under the control ofa multiplexer (MUX) 150 and an OR gate 152. The MUX 150 has twoselectable inputs A and B which are under the control of a select inputS. Bit 7 of the command register CMD₋₋ REG is applied to the selectinputs of the MUX 150 to control the mode of operation. As mentionedabove, when bit 7 of the command register CMD₋₋ REG[7:0] is set, thisindicates that the indexed mode of operation has been selected. If bit 0in the mask register MASK₋₋ REG[7:0] is also set, the programmableselect logic 7 will operate in the sticky mode of operation. Bit 7 ofthe command register CMD₋₋ REG[7:0] is applied to the select input S ofthe MUX 150. When this select input S is high, the MUX 150 selects inputB to enable either the index mode of operation or the sticky mode ofoperation. When the select input S is low, input A is selected for theaddress mode of operation.

When the address mode of operation is selected, the address selectsignal ADD₋₋ SEL is asserted on a successful address decode. This signalADD₋₋ SEL is under the control of an AND gate 154. The AND gate 154 is atwo-input AND gate. One input to the AND gate 154 is an address matchsignal ADD₋₋ MTCH from the ADD MATCH control logic 156. The other signalis an option match signal OPT₋₋ MTCH from the command match logic CMD₋₋MTCH 158. As will be discussed in more detail below, the ADD₋₋ MTCHsignal is asserted when an address matches the programmed address. Thisaddress match signal ADD₋₋ MTCH is qualified with the option matchsignal OPT₋₋ MTCH from the command match logic CMD₋₋ MTCH 158 such thatthe I/O select output signal IOSEL is only asserted for variousprogrammed commands, such as SECURE, WRITE, READ, or other qualifiers,such as a PRIVY signal, which, in turn, enable the AND gate 154 which,in turn, is applied to the A input of the MUX 150 to provide the I/Oselect output signal.

If the programmable select logic 7 is in an index mode of operation, bit7 of the command register CMD₋₋ REG[7:0] will select input B of the MUX150 to disable the address mode of operation. Input B of the MUX 150 isused for both the index node of operation and the sticky mode ofoperation. Whether the index mode of operation or the sticky mode ofoperation is selected is under the control of the OR gate 152, whoseoutput is applied to the B input of the MUX 150. In both an index andsticky mode of operation, the B input of the MUX 150 is selected. Whenthe "sticky" bit is set, the particular IOSEL is selected until the"sticky" bit is deasserted.

In an index mode of operation, the IOSEL signal is under the control ofthe AND gate 160. In a sticky mode of operation, the "sticky" bit (e.g.,bit 7 of the command register CMD₋₋ REG[7:0]) masks the index selectsignal INDEX₋₋ SEL such that the IOSEL signal is asserted as long as bit7 of the command register CMD₋₋ REG[7:0] is asserted. The index selectsignal INDEX₋₋ SEL is under the control of an AND gate 160. One input tothe AND gate 160 is the option match signal OPT₋₋ MTCH from the commandmatch logic CMD₋₋ MTCH 158. The other input to the AND gate 160 is anindex match signal INDEX₋₋ MTCH from the index control logic INDX₋₋ MTCH162. As will be discussed in more detail below, when the index matchesthe programmed index, the index match INDEX₋₋ MTCH signal will beasserted to enable the AND gate 160.

The programmable device 2 is thus adapted to decode either physical orindexed addresses. A physical address defines an actual I/O addresswithin the physical address space. An indexed address refers to a methodwhere the address is generated using a base address and an offset. Theindex values are available at the index register 90 and decoded asdiscussed below. The indexed decodes allow I/O devices to avoid usingany physical address space.

When an address mode is selected, the address can be fully decoded using16 bits of address or the lower eight address bits can be selectivelymasked off to enable up to 256 contiguous addresses to match the decode.This allows for global address ranges for option boards if necessary.

The programmable select logic 7 system is also able to provide an ISAbus slave signal I/O 16 which indicates to the system bus 3 that the I/Odevices 11, 12 on the expansion card 13 is capable of 16-bit datatransfers. This signal I/O 16 is available at the output of an AND gate164. One input to the AND gate 164 is the address select signal ADD₋₋SEL. Bit 0 of the command register is applied to the other input. Thisbit CMD₋₋ REG[0] is used to enable or disable the I/O 16 output.

The address match ADD₋₋ MTCH logic 156 is illustrated in FIG. 4. Thislogic 156 includes 16 exclusive NOR gates 166 through 196, 8 OR gates198 to 212, 2 NAND gates 214 and 216, and one NOR gate 218. The upperbyte of the system address ADDRESS[15:8] is applied to one input of theexclusive NOR gates 166 through 180. The eight bits of upper addressregister UADD₋₋ REG[7:0] are applied to the other inputs. The outputs ofthe exclusive NOR gates 166 to 180 are applied as inputs to NAND gate214 whose output is applied to NOR gate 218. The output of the NOR gate218 is the address match signal ADD₋₋ MTCH.

The lower byte of the system address ADDRESS[7:0] is applied to oneinput of the exclusive NOR gates 182 to 196. Bits 0 to 7 of the loweraddress register LADD₋₋ REG are applied to the other inputs. The outputsof the exclusive NOR gates 182 to 196 are applied to one input of the ORgates 198 through 212. The MASK₋₋ REG bits 0 to 7 are applied to theother inputs of the OR gates 198 to 212. The outputs of the OR gates 198to 212 are applied to the NAND gate 216 whose output is applied to theNOR gate 218.

When the ADDRESS from the system address bus matches the programmedaddress in the upper address register UADD₋₋ REG and the lower addressregister LADD₋₋ REG, the outputs of the exclusive NOR gates 166 through196 will be high. The high output from the exclusive NOR gates 166 to180 will cause the output of the NAND gate 214 to be low. When theaddress match logic ADD₋₋ MTCH 156 is decoding a single address, thebits 0 through 7 of the mask register MASK₋₋ REG will be deasserted. Inthis situation, the outputs of the exclusive NOR gates 182 to 196 areused to enable the NOR gates 198 to 212 to cause the output of the NANDgate 216 to be low, which in turn enables the address match signal ADD₋₋MTCH.

The mask register MASK₋₋ REG[7:0] enables a range of addresses to bedecoded. In particular, the mask register MASK₋₋ REG[7:0] controls theoutputs of the OR gates 198 through 212. When these bits are enabled,they will force the corresponding outputs of the OR gates 198 to 212 tobe high, which, in turn, results in the corresponding address bits beingignored. A summation of all of the mask register bits MASK₋₋ REG[7:0]being asserted results in the NAND gate 216 being deasserted. When themask register bits MASK₋₋ REG[7:0] are low, the lower byte address bitsare decoded in the same manner as the upper byte address bits.

The command match CMD₋₋ MTCH logic 158 is illustrated in FIG. 5 andincludes the NAND gates 216 through 228, the AND gate 232, the inverter230, and the OR gate 231. In an address decode mode of operation and anindex decode mode of operation, the command match CMD₋₋ MTCH logic 158is used to enable the output signals address select ADD₋₋ SEL and indexselect INDX₋₋ SEL (FIG. 3). As discussed above, additional qualifierscan be added, such that the I/O devices 11 and 12 will only be selectedon the expansion card 13 when the system controller 1 matches both thepreprogrammed address and the particular command programmed into thecommand register CMD₋₋ REG[7:0] for a particular I/O device 11, 12. Inparticular, bits 0, 2 through 4 from the command register CMD₋₋ REG[7:0]are applied to the inputs of the NAND gates 216 through 228. Bits 3 and4 are also applied to the OR gate 231. The WRITE, READ, and otherqualifier command signals, such as QUAL₋₋ A, are applied as inputs ofthe NAND gates 218, 220, 222, and 228. The SECURE signal is applied tothe input of the NAND gate 218 by way of the inverter 230. The outputsof the NAND gates 218 and 228 are applied as inputs to the NAND gates216 and 226, respectively, along with the bits 2 and 0 of the commandregister CMD₋₋ REG. The outputs of the NAND gates 220, 222 and OR gate231 are applied as inputs to the NAND gate 224. The outputs of the NANDgates 216, 224, and 226 are applied as inputs to the NAND gate 232. Theoutput of the NAND gate 232 is the option match signal OPT₋₋ MTCH.

In operation, when a command such as READ or WRITE matches thepreprogrammed command qualifier in the command register CMD₋₋ REG[7:0],the NAND gate 232 will be enabled, which, in turn, will enable the ANDgates 154 and 160 (FIG. 3) to enable the I/O select signals IOSEL duringan address and index mode of operation. During a sticky bit mode ofoperation, the command match CMD₋₋ MTCH logic 158 is ignored.

The index match INDX₋₋ MTCH logic 162 is illustrated in FIG. 6 andincludes the inverters 234 and 236 and the AND gates 238 to 240. Theindex match logic INDX₋₋ MTCH 162 is used to enable the AND gate 160(FIG. 3), which, in turn, is used in an index mode of operation. Thevalue from the index register 90 (FIG. 2) is applied to the inputs ofthe AND gate 238 with bits 1 and 7 of the index register 90 beinginverted by inverters 234 and 236. The output of the AND gate 238 isapplied to one input of the AND gate 240 along with the data decodesignal DATA₋₋ DEC. The AND gate 238 decodes the index value written tothe index register 90 (FIG. 2).

The signal DATA₋₋ DEC (FIG. 2) is available at the output of the OR gate130 and is enabled whenever system controller 1 initiates a read orwrite access to the port. When both the output of the AND gate 238 isasserted along with the data decode signal DATA₋₋ DEC, the index matchsignal INDX₋₋ MTCH goes high.

Remapping of IRQ and DMA Control Lines

To provide flexibility and alleviate the burdens of knowing the detailsof microcomputer system resources and hardware locations, the embodimentuses a hardware method to provide a system having means for remappinginput I/O lines to any one or more output I/O lines under softwarecontrol. The embodiment includes mapping interrupt requests (IRQs) anddirect memory access (DMA) I/O channel control lines to multiple outputdestinations. Since in many cases the complexity of a microcomputerconfiguration is directly related to the multiplexing of the interruptand DMA I/O channel control lines, this complexity may be reducedconsiderably by eliminating the need for physical jumpers manuallyplaced by the user when configuring the system for use with deviceswhich use the interrupt and DMA I/O channels.

The use of jumpers is burdensome and often confusing to users. In fact,improper jumper configuration often creates system conflicts which,through the eyes of the novice user, often looks like softwareincompatibility issues when in fact the problem actually only lies inthe improper hardware jumper configuration. Microcomputer systems havetypically been built with a confusing matrix of these hardware jumpersand complex related documentation which is also confusing. Differentmotherboards and add-on cards have added to the confusion by placingthese hardware jumpers in different locations depending on theparticular product. Moreover, if a resource limit is reached because toomany different jumper options have been used up, then some add-on boardsor system options may not be available to the user. All this hashistorically left users confused with how interrupts and DMA I/O controllines should be configured. Accordingly, the elimination of physicaljumpers as provided by the embodiment considerably reduces thecomplexity and user confusion associated with interrupt and DMA I/Ocontrol line configuration.

The embodiment provides programmable DMA switching of six (6) differentpairs of DMA control lines to be mapped to three (3) different sources.The embodiment also provides for the programmable switching of six (6)IRQ IN lines to any of six (6) IRQ OUT lines. Of course, the mapping ofthree (3) DMA input pairs to six (6) output pairs and the mapping of six(6) IRQ input lines to six (6) IRQ output lines is only an arbitrarychoice for the embodiment; any number of input and output I/O controllines could be switched in accordance with the invention (2 channels,e.g., 0,1, are shown in FIG. 1 for the interrupt and DMA control lines).As will be described in more detail below, switching is provided by theprogrammable device 2 through a series of registers which controlmultiplexers (MUXs) and demultiplexers (DEMUXs) which carry out theswitching of the control lines. The registers reside in the registerfile 6 as described above. The programmable device 2 is disposed betweenthe system controller 1 via the system bus 3 and the option card 13 tofacilitate I/O communications with baby card control and support I/Odevices 11, 12 over interrupt and DMA I/O channels. DMArequest/acknowledging mapping logic 10 utilizes MUXs and DEMUXs as wellas associated glue logic which is described below. The interrupt mappinglogic 9 uses DEMUXs and associated glue logic described below.

DMA Mapping Logic

In order to make the system as integrated as possible, the programmabledevice 2 controls all system I/O functions, controls the I/O data paths,and routes signals critical to the DMA and IRQ paths. The mappingcontrol logic is normally programmed by the system firmware during thepower-up sequence to industry standard location which may bereprogrammed later under software control. Referring again to FIG. 1, itcan be seen that the system address bus and the XDATA bus are bothconnected to the register file 6 within the programmable device 2. Theregister file 6 contains numerous READ and WRITE 8-bit registers, six ofwhich are of interest in the present discussion, namely, the three DMAregisters and the three IRQ registers. All of these registers areaccessed by an indexing mechanism which is controlled through twoaddress locations within the system's real I/O address space, asdescribed above.

FIG. 2 shows the register file wherein the registers for DMA switchingof DMA channel 1 and channel 0, channel 3 and channel 2, and channel 5and channel 4, DMASW10₋₋ REG, DMASW32₋₋ REG, and DMASW54₋₋ REG,respectively, are programmable registers controlling DMA requestacknowledging mapping logic 10. The location of the registers in theembodiment are at index x045, x046, and x047 ports respectively. Theregisters for interrupt request switching of interrupt channel 1 andchannel 0, channel 3 and channel 2, and channel 5 and channel 4,IRQSW10₋₋ REG, IRQSW32₋₋ REG, and IRQSW54₋₋ REG, respectively, are theregisters controlling the interrupt mapping logic 9 which is located atindex x041, x042, and x043 ports respectively, in the embodiment. Theinterrupt and DMA I/O channel control registers are written to underprogram control by indexing in data transfer to the programmable device2, as described above.

Each of the six interrupt and DMA control registers are 8-bit latcheswherein each byte comprises a low nibble and a high nibble, and eachnibble controls an I/O channel (DMA control line pair or interruptcontrol line). The DMA and interrupt control lines are numbered from 0to 5, wherein each number represents a DMA control line pair comprisinga DMA request signal line (DRQ) and a DMA acknowledge signal line (DACK)in the case of a DMA channel, and represents an interrupt request (IRQ)line in the case of an interrupt channel.

FIG. 7 represents the first DMA mapping switch register from theregister file 6. As can be seen from FIG. 7, the DMA mapping switchregisters control two sets of DMA channel control line pairs each. TheDMA switch register shown in FIG. 7 is DMASW10₋₋ REG which controls DMAinput channel 0 and DMA input channel 1. The control circuitry shown inFIG. 7 routes either DMA input channel to any one of DMA output channels0,1, or 2.

The following TABLE 1 represents the programming of the data byterepresented by the DMA switch registers.

                                      TABLE 1                                     __________________________________________________________________________    DMA.sub.-- SWITCH REGISTER                                                    __________________________________________________________________________    Register(s)                                                                            DMA.sub.-- SWITCH.sub.-- 1.sub.-- 0                                           DMA.sub.-- SWITCH.sub.-- 3.sub.-- 2                                           DMA.sub.-- SWITCH.sub.-- 5.sub.-- 4                                  Index(s) x045 for DMA.sub.-- SWITCH.sub.-- 1.sub.-- 0                                  x046 for DMA.sub.-- SWITCH.sub.-- 3.sub.-- 2                                  x047 for DMA.sub.-- SWITCH.sub.-- 5.sub.-- 4                         Mode     Read/Write                                                           Description                                                                            These registers control the DRQ.sub.-- OUT and DACK.sub.-- IN                 pins. They                                                                    control which device DRQ.sub.-- IN and DACK.sub.-- OUT should be              assigned to                                                                   each bus DRQ.sub.-- OUT and DACK.sub.-- IN. Each half register                is associated                                                                 with the bus side pins. For example, DMA.sub.-- SWITCH.sub.--                 5.sub.-- 4                                                                    determines the settings for the DMA.sub.-- OUT[5] and                         DACK.sub.-- IN[5] pins                                                        and for the DMA.sub.-- OUT[4] and DACK.sub.-- IN[4] pins.            Bits   7     6  5   4  3     2  1   0                                         Fields XBUS.sub.-- CNTRL.sub.-- 1                                                             DEV.sub.-- SEL.sub.-- 1                                                              XBUS.sub.-- CNTRL.sub.-- 0                                                             DEV.sub.-- SEL.sub.-- O                       Reset State                                                                          reserved                                                                            X  X   X  reserved                                                                            X  X   X                                         (DMA.sub.-- SWITCH.sub.-- 1.sub.-- 0 shown)                                   Field Description                                                             DEV.sub.-- SEL.sub.-- X                                                                This field selects which device DRQ.sub.-- OUT[N] and returning               DACK.sub.-- IN[N] will use this DRQ.sub.-- OUT[X] DACK.sub.--                 IN[X] (X =                                                                    register half number, N = sel value):                                         DEV.sub.-- SEL.sub.-- 0 = 00 connects DRQ.sub.-- IN[0] to the                 DRQ.sub.-- OUT[0] and                                                         DACK.sub.-- IN[0] to DACK.sub.-- OUT[0].                                      DEV.sub.-- SEL.sub.-- 0 = 01 connects DRQ.sub.-- IN[1] to the                 DRQ.sub.-- OUT[0] and                                                         DACK.sub.-- IN[0] to DACK.sub.-- OUT[1].                                      DEV.sub.-- SEL.sub.-- 0 = 10 connects DRQ.sub.-- IN[2] to the                 DRQ.sub.-- OUT[0] and                                                         DACK.sub.-- IN[0] to DACK.sub.-- OUT[2].                                      DEV.sub.-- SEL.sub.-- 0 = 11 unused combination disables                      DRQ.sub.-- OUT[0]. The                                                        DACK.sub.-- IN[0] will continue to control the XBUSes as                      configured.                                                          XBUS.sub.-- CNTRL.sub.-- X                                                             This field determines whether XBUS control lines will be used                 during                                                                        the DACK.sub.-- IN[X].                                               __________________________________________________________________________

As can be seen in FIG. 7, the data byte contained in the DMA switchregister shown in TABLE 1 is used to configure the multiplexer anddemultiplexer circuitry of FIG. 7 as well as the XBUS control circuitry,which includes DATA₋₋ READ from the OR gate 314 output to DATA₋₋ READ818 (FIG. 10). Only the first register (index x045) is illustrated inFIG. 7, however, the other registers are configured similarly for DMAI/O channels 2, 3 and 4, 5.

The DMA switch register for channels 0,1 according to TABLE 1 and FIG. 7programmed at offset x045 in register file 6 will control two of the sixDMA I/O control line pairs (DACK₋₋ IN0/DRQ₋₋ OUT0 and DACK₋₋ IN1/DRQ₋₋OUT1). The first two register bits 0,1 are for device select channel 0,DEV₋₋ SEL0 which controls the demultiplexing at DEMUX 301 of DACK₋₋ IN0to DACK₋₋ OUT0, DACK₋₋ OUT1, or DACK₋₋ OUT2. The first two register bits0,1, DEV₋₋ SEL0 also control the demultiplexing at MUX 302 of DRQ₋₋ IN0,DRQ₋₋ IN1, or DRQ₋₋ IN2 to DRQ₋₋ OUT0. DEMUX 301 and MUX 302 arecontrolled via control lines S0 and S1 from DEV₋₋ SEL0 in order tomultiplex and demultiplex the DMA I/O control line signals. Also, theoutput of DEMUX 301 and MUX 302 are tri-stated by the control lines S0and S1 by AND gate 303 by controlling tri-state buffers 304, 305, 306,and 307 as shown in FIG. 7. The DMA switching DEMUX 301 and MUX 302 plusglue logic is represented generally with the dashed line Box 310.Similarly, the upper nibble of the register of TABLE 1 and FIG. 7controls a DEMUX and MUX with a Box 312 similar to Box 310 to route DMAI/O control line signal paths for DMA channel 1.

XBUS₋₋ CNTL₋₋ 0 and XBUS₋₋ CNTL₋₋ 1 each respectively control the readenables for DMA channel 0 and DMA channel 1 access to the XBUS. AND gate308 "ands" XBUS control, CNTL₋₋ 0 with DMA acknowledge input 0 to createa read enable, READ0, which is "ored" at OR gate 314 with a read enable,READ1, from DMA I/O channel 1 to send DATA₋₋ READ via 818 (FIG. 10)which is described above in conjunction with XBUS control 8.

With DMA switching, in order to allow for six different lines to bemapped to three different sources with the above three registers on theprogrammable device 2, six DMA acknowledge IN lines are demultiplexed tothree DMA acknowledge OUT lines (e.g., DACKIN0 . . . DACKIN5 to DACK₋₋OUT0 . . . DACK₋₋ OUT2) as will become apparent in the discussion thatfollows.

DMA services provided on the motherboard and on add-on cards may accesssystem resources by becoming a bus user directly or via the DMAcontroller. The purpose of DMA services is to provide for the transferof data between I/O and memory using the DMA signals as a request to theDMA controller to obtain the bus and execute the transfer cycles. As oneskilled in the art appreciates, each DMA channel has two pairs of signallines which have already been introduced (1) "DRQ" for DMA request and(2) "DACK" for DMA acknowledge. The "DRQ and DACK" are the "pair" of DMAcontrol signal lines which are switched in the embodiment under programcontrol and without the use of physical jumpers. The DMA request, DRQsignal is driven by the I/O resources to request DMA service from theDMA controller. The DRQ signal will remain active until the controllerresponds with the appropriate DMA acknowledge, DACK signal.

The programmable DMA channel configuration provided by the embodimentmeets the configuration and software requirements for eachrequest/acknowledge pair (DRQ/DACK), providing a very dynamiccontrollable technique to select and direct where DMA I/O control linesare routed. In order to provide a programmable solution, the embodimentemploys the programmable device 2 which provides the requiredconfigurable DMA control line pairs for the entire system. Throughsoftware control the system interrupt and DMA resources may be mapped ordisabled to allow custom configuration of the system. The DRQ₋₋IN0-DRQ₋₋ IN2 input pins may be mapped to any one or more of the DRQ₋₋OUT0-DRQ₋₋ OUT5 output pins. The DRQ₋₋ OUT pins are tri-stated when notbeing used by a DRQIN, allowing for an external device on the systemside to drive these lines. Since the DMA request works in pairs with theDMA acknowledge lines, the same DMA mapping circuitry also controls theinput pin DACK₋₋ IN0-DACK₋₋ IN5 to DACK₋₋ OUT0-DACK₋₋ OUT2. When aDACK₋₋ INX from the system side is asserted, the XBUS control block maybe used for the cycle, depending on how the DMASWXX₋₋ REG switchregister is configured. The XBUS may be used even though a DACKIN# isnot being used by any of the device channels.

FIG. 8A represents exemplary logic circuitry for implementing the DMAmapping DEMUX 301, and FIG. 8B shows a truth table relating where the INsignal will be routed according to S0 and S1 to OUT₋₋ 0, OUT₋₋ 1, OUT₋₋2, or OUT₋₋ 3. The circuitry represented by FIG. 8A and FIG. 8B showshow the control lines S0 and S1 affect the DEMUX 301 circuitry. Thecircuit of FIG. 8A provides for AND gates 356, 358, 360, and 362, eachhaving three inputs and one output. One of each of the inputs to the ANDgates 356, 358, 360, and 362 are provided by IN signal which is to berouted to one of the outputs of one of the AND gates 356, 358, 360, or362 at OUT₋₋ 0, OUT₋₋ 1, OUT₋₋ 2, or OUT₋₋ 3, respectively. Inverted andnoninverted versions of control lines S0 and S1 are each provided toinputs to AND gates 356, 358, 360, and 362. Inversion of control line S0is provided by inverter 352 and inversion of control line S1 is providedby inverter 354. Noninverted S0 control line signals are presented toAND gates 358 and 362 while inverted S0 signals are presented to ANDgates 356 and 360 via inverter 352. Noninverted S1 signals are presentedto AND gates 360 and 362 and inverted S1 signals are presented to ANDgates 356 and 358 via inverter 354. Accordingly, when S0 and S1 are lowfor example, IN will be routed to OUT₋₋ 0 via AND gate 356. The otherways in which the IN signal is routed through the circuitry with controllines S0 and S1 is represented by the truth table shown in FIG. 8B.

FIG. 9A represents exemplary circuitry for DMA mapping MUX 302, and FIG.9B represents truth table showing outputs indicating which inputs arerouted to the output signal OUT. The MUX 302 circuitry shown in FIG. 9Aillustrates how control lines S0 and S1 affect AND gates 406, 408, 410,and 412 to determine which of input signals IN₋₋ 0, IN₋₋ 1, IN₋₋ 2, orIN₋₋ 3 are routed to the output signal OUT of a four input OR gate 414.The multiplexing is accomplished by sending noninverted versions of S1to the input of AND gates 410 and 412, and sending inverted versions ofS1 to AND gates 406 and 408 via inverter 404. Noninverted S0 controlsignals are sent to AND gates 408 and 412, and inverted S0 signals aresent to AND gates 406 and 410 via inverter 402. The output mapping isillustrated in the truth table of FIG. 9B.

Interrupt Mapping Logic

Turning now to the interrupt request, IRQ I/O channel control lineswitching, FIG. 11A, shows an IRQ switch register and related circuitryfor remapping IRQ I/O control lines, and FIG. 11B expands the circuitryof FIG. 11A to provide mapping of m interrupt channels. Having describedabove the DMA I/O channel switching in detail, one skilled in the artwill realize that IRQ switching is merely a subset of the DMA switching.The demultiplexing used for the interrupt mapping logic is much the sameas that used for DMA request mapping logic. In fact, IRQ switching ismuch simpler than DMA switching because only one control signal needs tobe routed for IRQ mapping, whereas two control signals (request andacknowledge) had to be mapped for DMA mapping. Moreover, since the IRQsignal is only an output signal being presented to the microcomputer bydevices interrupting the microcomputer, only DEMUXs for demultiplexingIRQ control line signals are required for switching. Multiplexing ofsignals returned from the microcomputer are not required in interruptmapping because no acknowledge signal is returned. The demultiplexercircuitry performed for IRQ mapping is much like the demultiplexingcircuitry provided by DEMUX 301 described above in the context of DMAmapping.

The IRQ mapping switch registers from the register file 6 controls two(2) sets of IRQ input lines each, thus three (3) registers are requiredto control six (6) IRQ input lines. The six registers utilized areIRQSW10₋₋ REG, IRQSW32₋₋ REG, and IRQSW54₋₋ REG located at data offsetx041, x042, and x043, respectively. The six IRQ channel inputscontrolled by the three registers are 0,1 and 2,3, and 4,5,respectively.

The following TABLE 2 represents the programming byte of the IRQ₋₋ IN₋₋SWITCH register.

                  TABLE 2                                                         ______________________________________                                        IRQ.sub.-- IN.sub.-- SWITCH REGISTER                                          ______________________________________                                        Register(s)                                                                           IRQ.sub.-- IN.sub.-- SWITCH.sub.-- 1.sub.-- 0                                 IRQ.sub.-- IN.sub.-- SWITCH.sub.-- 3.sub.-- 2                                 IRQ.sub.-- IN.sub.-- SWITCH.sub.-- 5.sub.-- 4                         Index(s)                                                                              x041 for IRQ.sub.-- IN.sub.-- SWITCH.sub.-- 1.sub.-- 0                        x042 for IRQ.sub.-- IN.sub.-- SWITCH.sub.-- 3.sub.-- 2                        x043 for IRQ.sub.-- IN.sub.-- SWITCH.sub.-- 5.sub.-- 4                Mode    Read/Write                                                            Description                                                                           These registers contain the controls needed to select which                   IRQ.sub.-- OUT will be used for IRQ.sub.-- INX.                       Bits     7         6     5   4   3       2   1   0                            Fields   DISABLE1  IRQ1.sub.-- SEL                                                                         DISABLE0                                                                              IRQ0.sub.-- SEL                          Reset State                                                                            X         X     X   X   X       X   X   X                            (IRQ.sub.-- SWITCH.sub.-- 1.sub.-- 0 shown)                                   Field                                                                         Description                                                                   IRQX.sub.-- SEL                                                                       This field selects which IRQ.sub.-- IN[X] is switched to                      IRQ.sub.-- OUT[N]:                                                            IRQX.sub.-- SEL = 000 connects IRQ.sub.-- IN[X] to IRQ.sub.--                 OUT[0]                                                                        IRQX.sub.-- SEL = 001 connects IRQ.sub.-- IN[X] to IRQ.sub.--                 OUT[1]                                                                        IRQX.sub.-- SEL = 010 connects IRQ.sub.-- IN[X] to IRQ.sub.--                 OUT[2]                                                                        IRQX.sub.-- SEL = 011 connects IRQ.sub.-- IN[X] to IRQ.sub.--                 OUT[3]                                                                        IRQX.sub.-- SEL = 100 connects IRQ.sub.-- IN[X] to IRQ.sub.--                 OUT[4]                                                                        IRQX.sub.-- SEL = 101 connects IRQ.sub.-- IN[X] to IRQ.sub.--                 OUT[5]                                                                        EXAMPLE: If every IRQ.sub.-- SWITCH reg was loaded with                       00h then any IRQ.sub.-- IN would map to IRQ.sub.-- OUT[0].            DISABLEX                                                                              DISABLEX = 1 disables response to IRQ.sub.-- IN[X]                            (corresponding IRQ.sub.-- OUT will float if no other IRQ.sub.--               INs                                                                           are mapped to it)                                                     ______________________________________                                    

The register shown in TABLE 2 indicates the data byte programming of anyof the three above-described IRQ₋₋ IN₋₋ SWITCH registers which may beused for IRQ input channel mapping in accordance with the embodiment.The register shown in TABLE 2 indicates the data byte programming of anyof the three above-described IRQ₋₋ IN₋₋ SWITCH registers which may beused for IRQ input channel mapping in accordance with the embodiment.The data byte of TABLE 2 is shown in FIG. 11A as IRQ₋₋ IN₋₋ SWITCH₋₋ 10register controlling two demultiplexer circuits DEMUX 502 and DEMUX 506showing control of IRQ₋₋ OUT₋₋ 0 via NOR gate 504 and IRQ₋₋ OUT₋₋ 1 viaNOR gate 508. The IRQ mapping of FIG. 12A may be expanded to anarbitrary number m outputs in accordance with the invention asillustrated in FIG. 11B. <Disable, Select> correspond to bits in switchregister nibbles for programming DEMUXs 502, 506, and 512. Additional ORgates 510 and 514 are shown for added IRQ₋₋ OUT₋₋ X . . . IRQ₋₋ OUT₋₋ mcontrol lines.

As TABLE 2 and FIG. 11A illustrate, the 8-bit byte of an IRQSWXX₋₋ REGregister from register file 6 has an upper and lower nibble, each nibblecontrolling an IRQ I/O channel. As shown, control signals S0, S1, andDISABLE control the routing of an IRQ input signal to an IRQ outputdetermined by the demultiplexers DEMUX 502 and DEMUX 506, etc. The IRQmapping is programmed in register file 6 as described earlier and willcontrol two of the six IRQ input lines per register. Multiple inputs maybe programmed for a single output allowing the sharing of multiple IRQinput to enable a single IRQ output.

FIG. 12A shows circuitry for implementing DEMUX 502 or DEMUX 506. Thedemultiplexer logic circuitry in FIG. 12A is used to route the IN signalto one of four OUT signals, OUT₋₋ 0', OUT₋₋ 1', OUT₋₋ 2', or OUT₋₋ 3'.The demultiplexing circuitry of FIG. 12A is not unlike that of FIG. 8Afor the DMA control lines. However, the circuitry of FIG. 12A alsoincludes a disable which is inverted via inverter 564 and presented asan input to each of four AND gates 556, 558, 560, and 562. When disableis high its inverted signal, a low signal, is presented to the ANDgates, thus disabling their outputs by making them always low. Selectsignals S0' and S1' control the demultiplexing of the IN signal throughthe AND gates 556, 558, 560, and 562. Selection control is provided bypresenting the noninverted S0' signal to AND gate 558 and AND gate 562while presenting an inverted S0' to AND gate 556 and AND gate 560 viainverter 552. The noninverted S1' is presented to the input of AND gate560 and AND gate 562 while inverted S1' signals are presented to theinputs of AND gate 556 and AND gate 558 via inverter 554. The resultingsignal flow of the IN signal through the demultiplexer circuitry of FIG.12A is represented by the truth table shown in FIG. 12B.

FIGS. 13A and 13B are tables which are useful for programming theabove-described hardware for remapping of IRQ and DMA control lineswithout hardware jumpers. FIG. 13A is used for programming the DMAremapping wherein the six control line pairs (DRQ₋₋ OUT/DACK₋₋ IN) forthe Bus DMA channel are represented in the first column as 0 through 5.The device DMA channel is recorded in the second column (DRQ₋₋IN/-DACK₋₋ OUT). XBUS use is recorded in the third column and indicatedas on or off. The fourth column records the DMA switch registers for DMAchannels O,1 or 2,3 or 4,5, which are programmed as discussed above.FIG. 13B is used for remapping of IRQ control lines, wherein systemrequirements are recorded for the six IRQ channels (0-5) in the firstthree columns and register values for programming are stored in the lasttwo columns of the IRQ table.

Programmable Data Hold Control

In a computer system with multiple buses, it is advantageous toelectrically isolate the buses from each other. In the preferredembodiment, the system bus 3 is isolated from the option bus 13 by adata transceiver 5. The data transceiver 5 includes a write driver 14and a read driver 13. The write driver 14 drives data toward the optionbus 13 during write operations, and is controlled by a write enablesignal XWRITE₋₋ EN#. The read driver 13 drives data toward the systembus 3 during read operations, and is controlled by a read enable signalXREAD₋₋ EN#. The write enable signal XWRITE₋₋ EN# and the read enablesignal XREAD₋₋ EN# are controlled by XBUS control logic 8. The XBUScontrol logic 8 is shown in greater detail in FIG. 10. It is necessarythat write data become valid when, or shortly after, a write signalWRITE# begins and after the write signal WRITE# ends to ensure thatdevices respond to valid data when receiving the write signal WRITE#.Devices latch write data on the trailing edge of the write signalWRITE#. This makes it critical to maintain valid write data beyond theend of the write signal WRITE#. Therefore, the write enable signalXWRITE₋₋ EN# must remain active beyond the end of the write signalWRITE#, ensuring the write driver 14 continues to drive the write databeyond the end of the write signal WRITE#.

Referring to FIG. 10, all write signals 802 are provided to the inputsof OR gate 804. The output of OR gate 804 XWRITE is provided to OR gate806 and to a group of serially connected inverters 808. The output ofthe group of serially connected inverters 808 is provided to a group ofserially connected inverters 810 and to a MUX 814. The output of thegroup of serially connected inverters 810 is provided to a group ofserially connected inverters 812 and to the MUX 814. The output of thegroup of serially connected inverters 812 is provided to the MUX 814.Finally, the output of the MUX 814 is provided to an OR gate 806. TheMUX 814 provides the outputs of the groups of serially connectedinverters 808, 810, and 812 to the OR gate 806 in response to controllines 816. Each group of serially connected inverters 808 through 812delays its output by an incremental period. The duration of the writeenable signal XWRITE₋₋ EN# is controlled by enabling the outputs of thegroups of serially connected inverters 808 through 812. An OR of thewrite signal XWRITE and the output of the group of serially connectedinverters 808 will provide a signal of slightly longer duration than thewrite signal XWRITE itself. An OR of the write signal XWRITE and theoutput of the group of serially connected inverters 808 and the outputof the group of serially connected inverters 810 will provide a signalof longer duration than the combination of the write signal XWRITE andthe output of serially connected inverters 808. The combination of thewrite signal XWRITE, the output of the group of serially connectedinverters 808, the output of the group of serially connected inverters810, and the output of the group of serially connected inverters 812will provide the longest signal.

Referring to FIG. 17, timing diagram A demonstrates the typical timingon the system bus 3 of system data SYSDATA and the write signal WRITE#.The system data SYSDATA must be present and valid shortly after time T1and be continuously present and valid until after time T2. The writesignal WRITE# goes active (low) at time T1 and inactive (high) at timeT2. The write signal WRITE# informs a device that valid data is beingwritten to it. The device may accept the data anytime the write signalWRITE# is active and latch write data on the trailing edge of the writesignal WRITE#. It is important to note that a device may accept data upto thirty or forty nanoseconds after time T2 (the time the write signalWRITE# goes inactive) due to delays in the device's electricalcircuitry.

Timing diagram B demonstrates the problems encountered when the writesignal WRITE# is used to control the write driver 13 without the presentinvention. The XBUS data XDATA becomes valid shortly after the writeenable signal XWRITE₋₋ EN# becomes active (low). The XBUS data XDATAalso becomes invalid when the write enable signal XWRITE₋₋ EN# becomesinactive (high). If a slow device accepts the XBUS XDATA thirtynanoseconds after the write enable signal XWRITE₋₋ EN# becomes inactive,the device will accept invalid data.

Timing diagram C demonstrates the timing of a system incorporating thepresent invention. The XBUS data XDATA becomes valid at time T1, orshortly after time T1, when the write enable signal XWRITE₋₋ EN# becomesactive (low). The XBUS data XDATA becomes invalid when the write enablesignal XWRITE₋₋ EN# becomes inactive (high). The write signal XWRITE#informs a device when data is valid. The write enable signal XWRITE₋₋EN# is equivalent to write signal XWRITE# except that the time in whichit becomes inactive (high) is delayed by the delay circuit of FIG. 10.This ensures that the XBUS data XDATA will remain valid for thirty toforty nanoseconds after the write signal XWRITE# becomes inactive(high).

The duration of the delay between when the write enable signal XWRITE#becomes inactive (high) and the write enable signal XWRITE₋₋ EN# becomesinactive (high) is determined by the number of inverter gates employedin the delay circuit of FIG. 10. Differing considerations in theenvironment where the XBUS control 8 is used, determines the delaynecessary. By way of example, increased temperature tends to reduce theamount of delay required. A temperature sensor can be used to controlthe delay setting selected by the control signals 816. Some devicesrespond more quickly than others to write signals. A longer delay may beneeded in addressing slower devices than is needed in addressing fasterdevices. Also, some computer systems respond more quickly than others.Programmability of the delay device allows the delay device to beutilized in a wider range of computer systems. Some ASICS respond morequickly than others. Even within a given manufacturing lot, ASICS willvary in terms of the response time. An increased delay time can be usedwith faster responding ASICS. The preceding reasons for changing theprogram delay of the delay circuit of FIG. 10 are provided by way ofillustration. Numerous other factors in a complex computer environmentwill affect the optimum delay of the write enable signal.

Shadowed Write Only Port

I/O device 11 on option bus 13 includes a write only port. The writeonly port includes signals such as a signal to enable flash ROMprogramming, a reset of the numeric coprocessor, a change of the speedmode of the processor, and changes to the memory map. It is oftenadvantageous for the BIOS to be able to read the state of these signals,but they cannot be read directly from the write only port in the I/Odevice 11. The signals on the port in the I/O device 11 can only bechanged when the system is in the index mode. The write only port on theI/O device 11 is a transparent write only latch. A typical example of atransparent write only latch is the 74X373 series from TexasInstruments. The present invention provides a shadow register, or aregister that contains the same data as the write only port on the I/Odevice 11 while the system is in the index mode. The register 105 inFIG. 2 is normally used as the lower address decode register. However,the lower address decode register is not required when the system is inthe index mode. Since the register 105 is not needed as a lower addressdecode register in the index mode, it is advantageous to use theregister 105 as a shadow register for the write only port in the I/Odevice 11. This avoids the necessity of additional hardware. Further,access to the register 105 is controlled by the index register and bythe SECURE signal. This allows only the BIOS, or those programsauthorized by the BIOS, to either read from or write to the register105. When data is to be written to the write only port on the I/O device11, the data, the address of the write only port on the I/O device 11,and the write signal WRITE# are asserted on the system bus 3 by systemcontroller 1. The data is provided via the system bus 3 to the datatransceiver 5, and from the data transceiver 5 to the register file 6and to the option bus 13. The data is then presented to the programmableselect logic 7, and thereby, to registers 104 through 114. Thecombination of the write signal WRITE#, the address of the register 105,and the SECURE signal 4 to the data port decode logic 92, signals theregister select logic 93 to allow data to be written to the register105.

Specifically, once the programmable select logic 7 is programmed intothe indexed write mode, and the register select decode logic 92 containsthe address of the register 105, the system controller 1 generates theaddress of the write only port on the I/O device 11 which is applied tothe register file 6 and the programmable select logic 7 by the systembus 3. The data simultaneously generated by the system controller 1 isapplied to the register file 6 through the system bus 3, the datatransceiver 5, and the option bus 13. Simultaneously, the systemcontroller 1 also generates the write signal WRITE# which is applied tothe programmable select logic 7. The data port decode logic 92 and theregister select logic 93 decode the address as the write signal WRITE#goes active (low). The write signal WRITE# in turn drives the the I/Oselect signal IOSELO# low. The active I/O select signal IOSELO# puts thewrite only port on the I/O device 11 into transparent mode to read data.When the system controller 1 deactivates the write signal WRITE# (high),the programmable select logic 7 drives the I/O select signal IOSELO#inactive (high) as well. The XDATA will be latched into the write onlyport on the I/O device 11. Simultaneously, the data is written to theregister 105. The data port decode logic 92 and the register selectlogic 93 address lower address decode register 105 by asserting thetarget register signal 116. The target register signal 116 prepares theregister 105 to latch the XDATA. When the system controller 1 deassertsthe write signal WRITE#, the target register signal 116 is deassertedand the register 105 latches the data. Thus, the data latched in thewrite only port on the I/O device 11 is identical to the data latched inregister 105.

Therefore, in response to the write signal WRITE#, the data will bewritten to both register 105 and the write only port on the I/O device11. When data is to be read back from the write only port on the I/Odevice 11, the address of the register 105 is written into the registerselect logic 93 to select the register 105 as the target of the next I/Ocycle. Then a read cycle to the data port is initiated which assertsIOSEL0 to the I/O device 11 and the read signal READ# will be assertedon the system bus 3 by the system controller 1. The write only port onthe I/O device 11 will not respond since it is a write only port and thedevice attempting to read from the write only port on the I/O device 11will receive a signal of all ones. This is the same signal as would bereceived if no I/O device 11 exists.

When data is to be read from register 105, the system controller 1asserts the read signal READ# active (low). Since the I/O select signalIOSELO# is a write only signal, it will remain inactive (high). Thesystem controller 1 asserts an address signal to the data port decodelogic 92 via the system bus 3. The data port decode logic 92 in responseto the read signal READ#, and the SECURE signal, asserts a DATA₋₋ READsignal 131 active. The index register 90, having been previouslyprogrammed to point to the register 105, asserts a signal to the MUX 130to select the output of the register 105. The DATA₋₋ READ signal 131 isalso applied to the AND gate 133 along with the value in bit 7 of theindex register 90. The output of the AND gate 133 enables a tri-statedevice 129 to receive data from the MUX 130.

However, if the read signal and the address of the write only port onthe I/O device 11 are asserted with the SECURE signal, the data portdecode logic 92 and the register select logic 93 will cause the MUX 130to not present the data in the register 105.

This provides maximum security for the write only port on the I/O device11 since a device not authorized by the BIOS to read the register 105cannot even determine if the I/O device 11 exists. The invention is mostuseful where the values in a write only port are critical to systemfunction. In many cases, a read of a register will cause a momentaryfluctuation in the value in that register. If user applications areallowed to read register containing critical system control signals,fluctuations in the output signals could be modified at times whichcould cause damage to the system. In the present invention, not evenreads by the BIOS will cause such fluctuations in a protected write onlyport since reads are applied to the register 105 rather than the writeonly port.

Security Of I/O Controller

Security from data loss to or data modification by peripheral devices isprovided by control of the peripheral device interrupts. By readingperipheral devices physically connected to the system and blocking theinterrupts, the system can access the peripheral devices but not allowthe peripheral devices to take control of or interrupt the system.Secure switch 4 in FIG. 1 is shown as a simple key switch. It should beclear to one of skill in the art that the security switch can beprovided for by numerous devices capable of providing security such as akey switch, a magnetic card reader, a personal identification number, anencrypted software key, hand scanner, a voice recognition device, otherdevices which identify the authority of the user asserting the securefunction, on any combination of the above.

The output of the secure switch 4 is applied to the data port decodelogic 92. The secure signal must be active before any output on thelines 102 or 131 from the data port decode logic 92 is possible. Thisprevents any of the registers 104 through 114 in the register file 6from being read from or written to unless the SECURE signal isdeasserted.

Register 114 contains a bit mask identifying interrupts that should beblocked with the SECURE signal. The circuit of FIG. 14 is replicatedeight times, one for each bit in the register 114. An interrupt request652 is the output of an AND gate 654. The AND gate 654 receives inputfrom an interrupt request 656 and an OR gate 658. The OR gate 658receives its input from the secure switch 4 via an inverter 660 and therelevant bit from the interrupt secure register 114 via an inverter 662.

Thus, output signal request OUT 652 is a function of (1) a request toactivate that interrupt signal was made, and (2) that the SECURE signalis either inactive, or the input channel control was not programmed todisable the channel when the SECURE signal is active. The SECUREinteraction is as fundamental to the assembly as the actual externalrequest signal to generate the interrupt.

Referring to FIG. 15, the select match signal SEL₋₋ MTCH is the outputof an AND gate 704. The AND gate 704 receives input from OR gates 706,708, and 710. The OR gate 706 receives its input from an AND gate 712and an AND gate 714. The AND gate 712 receives its input from the addmatch circuit 106 and the index bit, bit 7, of the command register 107.The AND gate 714 receives its input from the index bit, bit 7, of theregister 107 and the index match circuit 112. The OR gate 708 receivesits input from the secure switch 4 and the secure bit, bit 2, of thecommand register 107. The input to the OR gate 708 is NOT secure bit 2or NOT secure switch 4 AND secure bit 2. The OR gate 710 receives itsexternal input from the PRIVY bit, bit 1, of command register and theprivy signal PRIVY. The input of the OR gate 710 is not PRIVY and bit 1in command register 107, or PRIVY bit 1 in command register 107 and theexternal PRIVY signal. Thus, the select match signal SEL₋₋ MTCH is afunction of (1) one I/O channel selection indicating either direct orindirect addressing modes, (2) the SECURE signal active or the secureselect control is not programmed to disable the channel when the SECUREsignal is active, and (3) that the PRIVY signal is either active, or theselect control is not programmed to disable the channel when PRIVY isactive. Finally, the output select match signal SEL₋₋ MTCH and I/Oselect IOSEL, the output of MUX 150, are applied to an AND gate 716 toproduce an I/O select signal IOSEL# to the option bus 13. Hence, no I/Oselection on the option bus 13 is possible unless the select match SEL₋₋MTCH is active.

Referring to FIG. 16, the data write signal DATA₋₋ WRITE supplied toXBUS control logic 8 is a function of the secure switch 4, the datadecode signal DATA₋₋ DEC, and the I/O write signal IOW. The data writesignal DATA₋₋ WRITE supplied to XBUS control 8 to the output of the ANDgate 752. The inputs to the AND gate 752 include the output of inverter754 (the not SECURE signal, data decode signal DATA₋₋ DEC and I/O writesignal IOW). Thus, the data write signal DATA₋₋ WRITE supplied to XBUScontrol logic is a function of (1) I/O write signal IOW, (2) the addressof the programming data register (DATA₋₋ DEC), and (3) the SECURE signalbeing inactive.

Obviously, many modifications and variations of the present inventionare possible in light of the above teachings. Thus, it is to beunderstood that, within the scope of the appended claims, the inventionmay be practiced otherwise than as specifically described above.

    __________________________________________________________________________    1. `timescale 1 ns/10 ps                                                      2. `ifdef DEFINED                                                             3. `else                                                                      4. ///////////////////////////////////////////////////////////////////        5. // FILE: defines.h                                                         6. // DESCRIPTION:                                                            7. // This file sets all constant values used in both the CLIO design         8. // code and the verification code.                                         9. ///////////////////////////////////////////////////////////////////        10.                                                                              // define some useful constants                                               `define z8                                                                          8`hzz                                                                   `define z16                                                                         16`hzz                                                                  `define zeros                                                                       `h0                                                                     // define some of the fixed port locations                                    `define I.sub.-- PORT                                                                 16`hE0 // default index port address for clio                         `define D.sub.-- PORT                                                                 16`hE4 // default data port address for clio                          `define POST                                                                         8`h80                                                                            // LED IO Port                                                      `define DIAG                                                                         8`hF2                                                                            // Diagnostic IO Port                                               `define PRIVY.sub.-- ON                                                                  8`hFB // Privy ON IO Port                                       20.                                                                              `define PRIVY.sub.-- OFF                                                                 8`hF9 // Privy OFF IO Port                                         `define KEY.sub.-- DATA                                                                  8`h60 //Keyboard IO Port                                           `define KEY.sub.-- STATUS                                                                8`h64 // Keyboard IO Port                                          `define RTC.sub.-- I                                                                     8`h70 // Real Time Clock IO Port                                   `define RTC.sub.-- D                                                                     8`h71 // Real Time Clock IO Port                                   `define CLRF                                                                             8`hF0 // Clear CoProccssor Error IO Port                           `define EID                                                                              16`hC83 // EISA ID IO Port                                         `define EID.sub.-- MASK                                                                  16`h003 // EISA IO IO Port Mask                                    // define all of the register index port values                               `define IOBASE.sub.-- DEFAULT 8`hE4                                        30.                                                                              `define SEL0CMD                                                                         8`h00                                                               `define SEL1CMD                                                                         8`h01                                                               `define SEL2CMD                                                                         8`h02                                                               `define SEL3CMD                                                                         8`h03                                                               `define SEL4CMD                                                                         8`h04                                                               `define SEL5CMD                                                                         8`h05                                                               `define SEL6CMD                                                                         8`h06                                                               `define SEL7CMD                                                                         8`h07                                                               `define SEL8CMD                                                                         8`h08                                                               `define SEL9CMD                                                                         8`h09                                                            40.                                                                              `define SEL10CMD                                                                        8`h0A                                                               `define SEL11CMD                                                                        8`h0B                                                               `define SEL12CMD                                                                        8`h0C                                                               `define SEL13CMD                                                                        8`h0D                                                               `define SEL14CMD                                                                        8`h0E                                                               `define SEL15CMD                                                                        8`h0F                                                               `define SEL0LADD                                                                        8`h10                                                               `define SEL1LADD                                                                        8`h11                                                               `define SEL2LADD                                                                        8`h12                                                               `define SEL3LADD                                                                        8`h13                                                            50.                                                                              `define SEL4LADD                                                                        8`h14                                                               `define SEL5LADD                                                                        8`h15                                                               `define SEL6LADD                                                                        8`h16                                                               `define SEL7AADD                                                                        8`h17                                                               `define SEL8LADD                                                                        8`h18                                                               `define SEL9LADD                                                                        8`h19                                                               `define SEL10LADD                                                                       8`h1A                                                               `define SEL11LADD                                                                       8`h1B                                                               `define SEL12LADD                                                                       8`h1C                                                               `define SEL13LADD                                                                       8`h1D                                                            60.                                                                              `define SEL14LADD                                                                       8`h1E                                                               `define SEL15LADD                                                                       8`h1F                                                               `define SEL0UADD                                                                        8`h20                                                               `define SEL1UADD                                                                        8`h21                                                               `define SEL2UADD                                                                        8`h22                                                               `define SEL3UADD                                                                        8`h23                                                               `define SEL4UADD                                                                        8`h24                                                               `define SEL5UADD                                                                        8`h25                                                               `define SEL6UADD                                                                        8`h26                                                               `define SEL7UADD                                                                        8`h27                                                            70.                                                                              `define SEL8UADD                                                                        8`h28                                                               `define SEL9UADD                                                                        8`h29                                                               `define SEL10UADD                                                                       8`h2A                                                               `define SEL11UADD                                                                       8`h2B                                                               `define SEL12UADD                                                                       8`h2C                                                               `define SEL13UADD                                                                       8`h2D                                                               `define SEL14UADD                                                                       8`h2E                                                               `define SEL15UADD                                                                       8`h2F                                                               `define SEL0MASK                                                                        8`h30                                                               `define SEL1MASK                                                                        8`h31                                                            80.                                                                              `define SEL2MASK                                                                        8`h32                                                               `define SEL3MASK                                                                        8`h33                                                               `define SEL4MASK                                                                        8`h34                                                               `define SEL5MASK                                                                        8`h35                                                               `define SEL6MASK                                                                        8`h36                                                               `define SEL7MASK                                                                        8`h37                                                               `define SEL8MASK                                                                        8`h38                                                               `define SEL9MASK                                                                        8`h39                                                               `define SEL10MASK                                                                       8`h3A                                                               `define SEL11MASK                                                                       8`h3B                                                            90.                                                                              `define SEL12MASK                                                                       8`h3C                                                               `define SEL13MASK                                                                       8`h3D                                                               `define SEL14MASK                                                                       8`h3E                                                               `define SEL15MASK                                                                       8`h3F                                                               `define FIXDIS                                                                          8`h40                                                               `define IRQSW10                                                                         8`h41                                                               `define IRQSW32                                                                         8`h42                                                               `define IRQSW54                                                                         8`h43                                                               `define IRQSEC                                                                          8`h44                                                               `define DMASW10                                                                         8`h45                                                            100.                                                                             `define DMASW32                                                                         8`h46                                                            101.                                                                             `define DMASW54                                                                         8`h47                                                            102.                                                                             `define IOBASE                                                                          8`h7F                                                            103.                                                                             `define DEFINED                                                            104.                                                                             `endif                                                                     105.                                                                             `include "defines.h" // comments                                           106.                                                                             ///////////////////////////////////////////////////////////////////        107.                                                                             // MODULE: BASEREG                                                         108.                                                                             // MODIFICATIONS:                                                          109.                                                                             //                                                                         110.                                                                             `define BASEREG.sub.-- REV 1.00                                            111.                                                                             //                                                                         112.                                                                             // DESCRIPTION: This module is just a register which resets to `hE4.       113.                                                                             // Data is written to it on the falling edge of the WR signal.             114.                                                                             // NOTE: This module uses the Toshiba structural element FD2               115.                                                                             module basereg (D.sub.-- IN, WR, RESET, D.sub.-- OUT);                     116.                                                                             input [7:0] D.sub.-- IN;                                                   117.                                                                             input   WR, RESET;                                                         118.                                                                             output [7:0] D.sub.-- OUT;                                                 119.                                                                             wire [7:0] D.sub.-- OUT;                                                   120.                                                                             wire SET=!RESET; // since the LD3 device has a low true reset              121.                                                                             wire NWR=!WR;                                                              122.                                                                             // latch connection allows an asynchronous reset to 0xE4 (IOBASE              DEFAULT)                                                                   123.                                                                             FD2 B7 (,D.sub.-- OUT[7],!D.sub.-- IN[7],NWR,SET);                         124.                                                                             FD2 B6 (,D.sub.-- OUT[6],!D.sub.-- IN[6],NWR,SET);                         125.                                                                             FD2 B5 (,D.sub.-- OUT[5],!D.sub.-- IN[5],NWR,SET);                         126.                                                                             FD2 B4 (D.sub.-- OUT[4],,D.sub.-- IN[4],NWR,SET);                          127.                                                                             FD2 B3 (D.sub.-- OUT[3],,D.sub.-- IN[3],NWR,SET);                          128.                                                                             FD2 B2 (,D.sub.-- OUT[2],!D.sub.-- IN[2],NWR,SET);                         129.                                                                             FD2 B1 (D.sub.-- OUT[1],,D.sub.-- IN[1],NWR,SET);                          130.                                                                             FD2 B0 (D.sub.-- OUT[0],,D.sub.-- IN[0],NWR,SET);                          131.                                                                             endmodule                                                                  132.                                                                             /* veri.sub.-- fix version 1.01 has been run on this file */               133.                                                                             module clio( AEN, DRQI, DRQO, IRQI, IRQO, N.sub.-- CLRF, N.sub.--             CSIN, N.sub.-- DIAG, N.sub.-- EID,                                         134. N.sub.-- FRCXRA, N.sub.-- FRCXW, N.sub.-- IO16, N.sub.-- IOR,                 N.sub.-- IOW, N.sub.-- KEY, N.sub.-- POST, N.sub.-- PRIVY,               135. N.sub.-- RESET, N.sub.-- RTC, N.sub.-- SECURE, N.sub.-- SL, N.sub.--          XREADA, N.sub.-- XREADB, N.sub.-- XWRITE,                                136. NDCKI, NDCKO, SA, XD );                                                  137.                                                                             input AEN;                                                                 138.                                                                             input [0:2] DRQI;                                                          139.                                                                             output [0:5] DRQO;                                                         140.                                                                             input [0:5] IRQI;                                                          141.                                                                             output [0:5] IRQO;                                                         142.                                                                             output N.sub.-- CLRF;                                                      143.                                                                             input N.sub.-- CSIN;                                                       144.                                                                             output N.sub.-- DIAG, N.sub.-- EID;                                        145.                                                                             input N.sub.-- FRCXRA, N.sub.-- FRCXW;                                     146.                                                                             output N.sub.-- IO16;                                                      147.                                                                             input N.sub.-- IOR, N.sub.-- IOW;                                          148.                                                                             output N.sub.-- KEY, N.sub.-- POST, N.sub.-- PRIVY;                        149.                                                                             input N.sub.-- RESET;                                                      150.                                                                             output N.sub.-- RTC;                                                       151.                                                                             input N.sub.-- SECURE;                                                     152.                                                                             output [0:15] N.sub.-- SL;                                                 153.                                                                             output N.sub.-- XREADA, N.sub.-- XREADB, N.sub.-- XWRITE;                  154.                                                                             input [0:5] NDCKI;                                                         155.                                                                             output [0:2] NDCKO;                                                        156.                                                                             input [0:15] SA;                                                           157.                                                                             inout [0:7] XD;                                                            158.                                                                             wire [2:0] DRQIN;                                                          159.                                                                             wire [5:0] IRQIN;                                                          160.                                                                             wire [5:0] DACKIN;                                                         161.                                                                             wire [15:0] ADD;                                                           162.                                                                             wire [7:0] D.sub.-- IN;                                                    163.                                                                             wire [5:0] DRQEN;                                                          164.                                                                             wire [5:0] IRQ.sub.-- OUT;                                                 165.                                                                             wire [2:0] DACK.sub.-- OUT;                                                166.                                                                             wire [15:0].sub.-- IOSEL;                                                  167.                                                                             wire [5:0] DRQOUT                                                          168.                                                                             wire [7:0] D.sub.-- OUT;                                                   169.                                                                             wire .sub.-- TEST1;                                                        170.                                                                             wire .sub.-- TEST2;                                                        171.                                                                             wire .sub.-- IO16;                                                         172.                                                                             wire .sub.-- PRIVY;                                                        173.                                                                             wire .sub.-- SEL.sub.-- CLRF;                                              174.                                                                             wire .sub.-- SEL.sub.-- DIAG;                                              175.                                                                             wire .sub.-- SEL.sub.-- EID;                                               176.                                                                             wire .sub.-- SEL.sub.-- KEY;                                               177.                                                                             wire .sub.-- SEL.sub.-- POST;                                              178.                                                                             wire .sub.-- SEL.sub.-- RTC;                                               179.                                                                             wire .sub.-- XREADA;                                                       180.                                                                             wire .sub.-- XREADB;                                                       181.                                                                             wire .sub.-- XWRITE;                                                       182.                                                                             wire .sub.-- D.sub.-- OE;                                                  183.                                                                             wire RESET;                                                                184.                                                                             wire IOW;                                                                  185.                                                                             wire IOR;                                                                  186.                                                                             wire FORCE.sub.-- XW;                                                      187.                                                                             wire FORCE.sub.-- XRA;                                                     188.                                                                             wire SEC;                                                                  189.                                                                             wire CS.sub.-- IN;                                                         190.                                                                             wire BAEN;                                                                 191.                                                                             core CORE ( ..sub.-- D.sub.-- OE(.sub.-- D.sub.-- OE), ..sub.--               DACK.sub.-- OUT(.sub.-- DACK.sub.-- OUT[0:2]),..sub.-- DRQ.sub.--             EN(.sub.-- DRQEN[0:5]),                                                    192. ..sub.-- IO16(IO16),..sub.-- IO.sub.-- SEL(.sub.-- IOSEL[0:15]),..sub         .-- IRQ.sub.-- OUT(.sub.-- IRQ.sub.-- OUT[0:5]),                         193. ..sub.-- PRIVY(.sub.-- PRIVY),..sub.-- SEL.sub.-- CLRF(.sub.--                SEL.sub.-- CLRF),..sub.-- SEL.sub.-- DIAG(.sub.-- SEL.sub.-- DIAG),      194. ..sub.-- SEL.sub.-- EID(.sub.-- SEL.sub.-- EID),..sub.-- SEL.sub.--           KEY(.sub.-- SEL.sub.-- KEY),..sub.-- SEL.sub.-- POST(.sub.--                  SEL.sub.-- POST),                                                        195. ..sub.-- SEL.sub.-- RTC(.sub.-- SEL.sub.-- RTC),..sub.-- TEST1(.sub.-         - TEST1),..sub.-- TEST2(.sub.-- TEST2),                                  196. ..sub.-- XREADA(.sub.-- XREADA),..sub.-- XREADB(.sub.-- XREADB),..sub         .-- XWRITE(.sub.-- XWRITE),                                              197. .ADD(ADD[0:15]),.AEN(BAEN),.CS.sub.-- IN(CS.sub.-- IN),.D.sub.--              IN(D.sub.-- IN[0:7]),                                                    198. .D.sub.-- OUT(D.sub.-- OUT[0:7]),.DACK.sub.-- IN(DACKIN[0:5]),.DRQ.su         b.-- IN(DRQIN[0:2]),                                                     199. .DRQ.sub.-- OUT(DRQOUT[0:5]),.FORCE.sub.-- XRA(FORCE.sub.-- XRA),.FOR         CE.sub.-- XW(FORCE.sub.-- XW),                                           200. .IOR(IOR),.IOW(IOW),.IRQ.sub.-- IN(IRQIN[0:5]),.RESET(RESET),            201. .SECURE(SEC));                                                           202.                                                                             TLCHTD PAEN(.A(AEN),.PI(1`b0), .Z(BAEN));                                  203.                                                                             TLCHTD PSA.sub.-- 0.sub.-- (.A(SA[15]),.PI(`b0),.Z(ADD[15]));              204.                                                                             TLCHTD PSA.sub.-- 1.sub.-- (.A(SA[14]),.PI(1`b0),.Z(ADD[14]));             205.                                                                             TLCHTD PSA.sub.-- 2.sub.-- (.A(SA[13]),.PI(1`b0),.Z(ADD[13]));             206.                                                                             TLCHTD PSA.sub.-- 3.sub.-- (.A(SA[12]),.PI(1`b0),.Z(ADD[12]));             207.                                                                             TLCHTD PSA.sub.-- 4.sub.-- (.A(SA[11]),.PI(1`b0),.Z(ADD[11]));             208.                                                                             TLCHTD PSA.sub.-- 5.sub.-- (.A(SA[10]),.PI(1`b0),.Z(ADD[10]));             209.                                                                             TLCHTD PSA.sub.-- 6.sub.-- (.A(SA[9]),.PI(1`b0),.Z(ADD[9]));               210.                                                                             TLCHTD PSA.sub.-- 7.sub.-- (.A(SA[8]),.PI(1`b0),.Z(ADD[8]));               211.                                                                             TLCHTD PSA.sub.-- 8.sub.-- (.A(SA[7]),.PI(1`b0),.Z(ADD[7]));               212.                                                                             TLCHTD PSA.sub.-- 9.sub.-- (.A(SA[6]),.PI(1`b0),.Z(ADD[6]));               213.                                                                             TLCHTD PSA.sub.-- 10.sub.-- (.(SA[5]),.PI(1`b0),.Z(ADD[5]));               214.                                                                             TLCHTD PSA.sub.-- 11.sub.-- (.A(SA[4]),.PI(1`b0),.Z(ADD[4]));              215.                                                                             TLCHTD PSA.sub.-- 12.sub.-- (.A(SA[3]),.PI(1`b0),.Z(ADD[3]));              216.                                                                             TLCHTD PSA.sub.-- 13.sub.-- (.A(SA[2]),.PI(1`b0),.Z(ADD[2]));              217.                                                                             TLCHTD PSA.sub.-- 14.sub.-- (.A(SA[1]),.PI(1`b0),.Z(ADD[1]));              218.                                                                             TLCHTD PSA.sub.-- 15.sub.-- (.A(SA[0]),.PI(1`b0),.Z(ADD[0]));              219.                                                                             TLCHTD PDRQIN.sub.-- 0.sub.-- (.A(DRQI[2]),.PI(1`b0),.Z(DRQIN[2]));        220.                                                                             TLCHTD PDRQIN.sub.-- 1.sub.-- (.A(DRQI[1]),.PI(1`b0),.Z(DRQIN[1]));        221.                                                                             TLCHTD PDRQIN.sub.-- 2.sub.-- (.A(DRQI[0]),.PI(1`b0),.Z(DRQIN[0]));        222.                                                                             TLCHNU PIRQIN.sub.-- 0.sub.-- (.A(IRQI[5]),.PI(1`b0),.Z(IRQIN[5]));        223.                                                                             TLCHNU PIRQIN.sub.-- 1.sub.-- (.A(IRQI[4]),.PI(1`b0),.Z(IRQIN[4]));        224.                                                                             TLCHNU PIRQIN.sub.-- 2.sub.-- (.A(IRQI[3]),.PI(1`b0),.Z(IRQIN[3]));        225.                                                                             TLCHNU PIRQIN.sub.-- 3.sub.-- (.A(IRQI[2]),.PI(1`b0),.Z(IRQIN[2]));        226.                                                                             TLCHNU PIRQIN.sub.-- 4.sub.-- (.A(IRQI[1]),.PI(1`b0),.Z(IRQIN[1]));        227.                                                                             TLCHNU PIRQIN.sub.-- 5.sub.-- (.A(IRQI[0]),.PI(1`b0),.Z(IRQIN[0]));        228.                                                                             TLCHNU PDACKIN.sub.-- 0.sub.-- (.A(NDCKI[5]),.PI(1`b0),.Z(DACKIN[5]));     229.                                                                             TLCHNU PDACKIN.sub.-- 1.sub.-- (.A(NDCKI[4]),.PI(1`b0),.Z(DACKIN[4]));     230.                                                                             TLCHNU PDACKIN.sub.-- 2.sub.-- (.A(NDCKI[3]),.PI(1`b0),.Z(DACKIN[3]));     231.                                                                             TLCHNU PDACKIN.sub.-- 3.sub.-- (.A(NDCKI[2]),.PI(1`b0),.Z(DACKIN[2]));     232.                                                                             TLCHNU PDACKIN.sub.-- 4.sub.-- (.A(NDCKI[1]),.PI(1`b0),.Z(DACKJN[1]));     233.                                                                             TLCHNU PDACKIN.sub.-- 5.sub.-- (.A(NDCKI[0]),.PI(1`b0),.Z(DACKIN[0]));     234.                                                                             TLCHNU PNCSIN(.A(N.sub.-- CSIN),.PI(1`b0),.Z(CS.sub.-- IN));               235.                                                                             TLCHNU PNSECURE(.A(N.sub.-- SECURE),.PI(1`b0),.Z(SEC));                    236.                                                                             TLCHNU PNFRCXRA(.A(N.sub.-- FRCXRA),.PI(1`b0),.Z(FORCE.sub.-- XRA));       237.                                                                             TLCHNU PNFRCXW(.A(N.sub.-- FRCXW),.PI(1`b0),.Z(FORCE.sub.-- XW));          238.                                                                             TLCHNU PNIOW(.A(N.sub.-- IOW),.PI(1`b0),.Z(IOW));                          239.                                                                             TLCHNU PNRESET(.A(N.sub.-- RESET),.PI(1`b0),.Z(RESET));                    240.                                                                             TLCHNU PNIOR(.A(N.sub.-- IOR),.PI(1`b0),.Z(IOR));                          241.                                                                             BT24 PNIO16(.A(1`b0),.EN(.sub.-- IO16),.TN(.sub.-- TEST2),.Z(N.sub.--         IO16));                                                                    242.                                                                             BT24RP PDRQOUT.sub.-- 0.sub.-- (.A(DRQOUT[5]),.EN(.sub.-- DRQEN[5]),.TN       (.sub.-- TEST1),.Z(DRQO[5]));                                              243.                                                                             BT24RP PDRQOUT.sub.-- 1.sub.-- (.A(DRQOUT[4]),.EN(.sub.-- DRQEN[4]),.TN       (.sub.-- TEST1),.Z(DRQO[4]));                                              244.                                                                             BT24RP PDRQOUT.sub.-- 2.sub.-- (.A(DRQOUT[3]),.EN(.sub.-- DRQEN[3]),.TN       (.sub.-- TEST1),.Z(DRQO[3]));                                              245.                                                                             BT24RP PDRQOUT.sub.-- 3.sub.-- (.A(DRQOUT[2]),.EN(.sub.-- DRQEN[2]),.TN       (.sub.-- TEST1),.Z(DRQO[2]));                                              246.                                                                             BT24RP PDRQOUT.sub.-- 4.sub.-- (.A(DRQOUT[1]),.EN(.sub.-- DRQEN[1]),.TN       (.sub.-- TEST1),.Z(DRQO[1]));                                              247.                                                                             BT24RP PDRQOUT.sub.-- 5.sub.-- (.A(DRQOUT[0]),.EN(.sub.-- DRQEN[0]),.TN       (.sub.-- TEST1),.Z(DRQO[0]));                                              248.                                                                             BT24RP PIRQOUT.sub.-- 0.sub.-- (.A(1`b0).,EN(.sub.-- IRQ.sub.--               OUT[5]),.TN(.sub.-- TEST1),.Z(IRQO[5]));                                   249.                                                                             BT24RP PIRQOUT.sub.-- 1.sub.-- (.A(1`b0).,EN(.sub.-- IRQ.sub.--               OUT[4]),.TN(.sub.-- TEST1),.Z(IRQO[4]));                                   250.                                                                             BT24RP PIRQOUT.sub.-- 2.sub.-- (.A(1`b0).,EN(.sub.-- IRQ.sub.--               OUT[3]),.TN(.sub.-- TEST1),.Z(IRQO[3]));                                   251.                                                                             BT24RP PIRQOUT.sub.-- 3.sub.-- (.A(1`b0).,EN(.sub.-- IRQ.sub.--               OUT[2]),.TN(.sub.-- TEST1),.Z(IRQO[2]));                                   252.                                                                             BT24RP PIRQOUT.sub.-- 4.sub.-- (.A(1`b0).,EN(.sub.-- IRQ.sub.--               OUT[1]),.TN(.sub.-- TEST1),.Z(IRQO[1]));                                   253.                                                                             BT24RP PIRQOUT.sub.-- 5.sub.-- (.A(1`b0).,EN(.sub.-- IRQ.sub.--               OUT[0]),.TN(.sub.-- TEST1),.Z(IRQO[0]));                                   254.                                                                             BT8RP PDACKO.sub.-- 0.sub.-- (.A(1`b0),.EN(.sub.-- DACK.sub.--                OUT[2]),.TN(.sub.-- TEST1),.Z(NDCKO[2]));                                  255.                                                                             BT8RP PDACKO.sub.-- 1.sub.-- (.A(1`b0),.EN(.sub.-- DACK.sub.--                OUT[1]),.TN(.sub.-- TEST1),.Z(NDCKO[1]));                                  256.                                                                             BT8RP PDACKO.sub.-- 2.sub.-- (.A(1`b0),.EN(.sub.-- DACK.sub.--                OUT[0]),.TN(.sub.-- TEST1),.Z(NDCKO[0]));                                  257.                                                                             BT8RP PNSEL.sub.-- 0.sub.-- (.A(.sub.-- IOSEL[15]),.EN(1`b0),.TN(.sub.-       - TEST2),.Z(N.sub.-- SL[15]));                                             258.                                                                             BT8RP PNSEL.sub.-- 1.sub.-- (.A(.sub.-- IOSEL[14]),.EN(1`b0),.TN(.sub.-       - TEST2),.Z(N.sub.-- SL[14]));                                             259.                                                                             BT8RP PNSEL.sub.-- 2.sub.-- (.A(.sub.-- IOSEL[13]),.EN(1`b0),.TN(.sub.-       - TEST2),.Z(N.sub.-- SL[13]));                                             260.                                                                             BT8RP PNSEL.sub.-- 3.sub.-- (.A(.sub.-- IOSEL[12]),.EN(1`b0),.TN(.sub.-       - TEST2),.Z(N.sub.-- SL[12]));                                             261.                                                                             BT8RP PNSEL.sub.-- 4.sub.-- (.A(.sub.-- IOSEL[11]),.EN(1`b0),.TN(.sub.-       - TEST2),.Z(N.sub.-- SL[11]));                                             262.                                                                             BT8RP PNSEL.sub.-- 5.sub.-- (.A(.sub.-- IOSEL[10]),.EN(1`b0),.TN(.sub.-       - TEST2),.Z(N.sub.-- SL[10]));                                             263.                                                                             BT8RP PNSEL.sub.-- 6.sub.-- (.A(.sub.-- IOSEL[9]),.EN(1`b0),.TN(.sub.--        TEST2),.Z(N.sub.-- SL[9]));                                               264.                                                                             BT8RP PNSEL.sub.-- 7.sub.-- (.A(.sub.-- IOSEL[8]),.EN(1`b0),.TN(.sub.--        TEST2),.Z(N.sub.-- SL[8]));                                               265.                                                                             BT8RP PNSEL.sub.-- 8.sub.-- (.A(.sub.-- IOSEL[7]),.EN(1`b0),.TN(.sub.--        TEST2),.Z(N.sub.-- SL[7]));                                               266.                                                                             BT8RP PNSEL.sub.-- 9.sub.-- (.A(.sub.-- IOSEL[6]),.EN(1`b0),.TN(.sub.--        TEST2),.Z(N.sub.-- SL[6]));                                               267.                                                                             BT8RP PNSEL.sub.-- 10.sub.-- (.A(.sub.-- IOSEL[5]),.EN(1`b0),.TN(.sub.-       - TEST2),.Z(N.sub.-- SL[5]));                                              268.                                                                             BT8RP PNSEL.sub.-- 11.sub.-- (.A(.sub.-- IOSEL[4]),.EN(1`b0),.TN(.sub.-       - TEST2),.Z(N.sub.-- SL[4]));                                              269.                                                                             BT8RP PNSEL.sub.-- 12.sub.-- (.A(.sub.-- IOSEL[3]),.EN(1`b0),.TN(.sub.-       - TEST2),.Z(N.sub.-- SL[3]));                                              270.                                                                             BT8RP PNSEL.sub.-- 13.sub.-- (.A(.sub.-- IOSEL[2]),.EN(1`b0),.TN(.sub.-       - TEST2),.Z(N.sub.-- SL[2]));                                              271.                                                                             BT8RP PNSEL.sub.-- 14.sub.-- (.A(.sub.-- IOSEL[1]),.EN(1`b0),.TN(.sub.-       - TEST2),.Z(N.sub.-- SL[1]));                                              272.                                                                             BT8RP PNSEL.sub.-- 15.sub.-- (.A(.sub.-- IOSEL[0]),.EN(1`b0),.TN(.sub.-       - TEST2),.Z(N.sub.-- SL[0]));                                              273.                                                                             BT8RP PNSRTC(.A(.sub.-- SEL.sub.-- RTC),.EN(1`b0),.TN(.sub.-- TEST2),.Z       (N.sub.-- RTC));                                                           274.                                                                             BT8RP PNSKEY(.A(.sub.-- SEL.sub.-- KEY),.EN(1`b0),.TN(.sub.-- TEST2),.Z       (N.sub.-- KEY));                                                           275.                                                                             BT8RP PNSDIAG(.A(.sub.-- SEL.sub.-- DIAG),.EN(1`b0),.TN(.sub.--               TEST2).,Z(N.sub.-- DIAG));                                                 276.                                                                             BT8RP PNPRIVY(.A(.sub.-- PRIVY),.EN(1`b0),.TN(.sub.-- TEST2),.Z(N.sub.-       - PRIVY));                                                                 277.                                                                             BT8RP PNSPOST(.A(.sub.-- SEL.sub.-- POST),.EN(1`b0),.TN(.sub.--               TEST2).,Z(N.sub.-- POST));                                                 278.                                                                             BT8RP PNSEID(.A(.sub.-- SEL.sub.-- EID),.EN(1`b0),.TN(.sub.-- TEST2),.Z       (N.sub.-- EID));                                                           279.                                                                             BT8RP PNSCLRF(.A(.sub.-- SEL.sub.-- CLRF),.EN(1`b0),.TN(.sub.--               TEST2),.Z(N.sub.-- CLRF));                                                 280.                                                                             BT12 PNXWRITE(.A(.sub.-- XWRITE),.EN(1`b0),.TN(.sub.-- TEST1),.Z(N.sub.       -- XWRITE));                                                               281.                                                                             BT8 PNXREADB(.A(.sub.-- XREADB),.EN(1`b0),.TN(TEST2),.Z(N.sub.--              XREADB));                                                                  282.                                                                             BT8 PNXREADA(.A(.sub.-- XRPADA),.EN(1`b0),.TN(TEST1),.Z(N.sub.--              XREADA));                                                                  283.                                                                             BD12TRP PXD.sub.-- 0.sub.-- (.A(D.sub.-- OUT[7]),.EN(.sub.-- D.sub.--         OE),.IO(XD[7]),.PI(1`b0),.TN(.sub.-- TEST1),                               284.                                                                             .ZI(D.sub.-- IN[7]));                                                      285.                                                                             BD12TRP PXD.sub.-- 1.sub.-- (.A(D.sub.-- OUT[6]),.EN(.sub.-- D.sub.--         OE),.IO(XD[6]),.PI(1`b0),.TN(.sub.-- TEST1),                               286.                                                                             .ZI(D.sub.-- IN[6]));                                                      287.                                                                             BD12TRP PXD.sub.-- 2.sub.-- (.A(D.sub.-- OUT[5]),.EN(.sub.-- D.sub.--         OE),.IO(XD[5]),.PI(1`b0),.TN(.sub.-- TEST1),                               288.                                                                             .ZI(D.sub.-- IN[5]));                                                      289.                                                                             BD12TRP PXD.sub.-- 3.sub.-- (.A(D.sub.-- OUT[4]),.EN(.sub.-- D.sub.--         OE),.IO(XD[4]),.PI(1`b0),.TN(.sub.-- TEST1),                               290.                                                                             .ZI(D.sub.-- IN[4]));                                                      291.                                                                             BD12TRP PXD.sub.-- 4.sub.-- (.A(D.sub.-- OUT[3]),.EN(.sub.-- D.sub.--         OE),.IO(XD[3]),.PI(1`b0),.TN(.sub.-- TEST1),                               292.                                                                             .ZI(D.sub.-- IN[3]));                                                      293.                                                                             BD12TRP PXD.sub.-- 5.sub.-- (.A(D.sub.-- OUT[2]),.EN(.sub.-- D.sub.--         OE),.IO(XD[2]),.PI(1`b0),.TN(.sub.-- TEST1),                               294.                                                                             .ZI(D.sub.-- IN[2]));                                                      295.                                                                             BD12TRP PXD.sub.-- 6.sub.-- (.A(D.sub.-- OUT[1]),.EN(.sub.-- D.sub.--         OE),.IO(XD[1]),.PI(1`b0),.TN(.sub.-- TEST1),                               296.                                                                             .ZI(D.sub.-- IN[1]));                                                      297.                                                                             BD12TRP PXD.sub.-- 7.sub.-- (.A(D.sub.-- OUT[0]),.EN(.sub.-- D.sub.--         OE),.IO(XD[0]),.PI(1`b0),.TN(.sub.-- TEST1),                               298.                                                                             .ZI(D.sub.-- IN[0]));                                                      299.                                                                             endmodule // clio                                                          300.                                                                             /* Verilog Net List from E.C.S. - File = CORE.v */                         301.                                                                             module core(ADD, AEN, CS.sub.-- IN, DACK.sub.-- IN, DRQ.sub.-- IN,            D.sub.-- IN, FORCE.sub.-- XRA,                                             302.                                                                             FORCE.sub.-- XW, IOR, IOW, IRQ.sub.-- IN, RESET, SECURE, DRQ.sub.--           OUT, D.sub.-- OUT,                                                         303.                                                                             .sub.-- DACK.sub.-- OUT, .sub.-- DRQ.sub.-- EN, .sub.-- D.sub.-- OE,          .sub.-- IO16, .sub.-- IO.sub.-- SEL, .sub.-- IRQ.sub.-- OUT, .sub.--          PRIVY,                                                                     304.                                                                             .sub.-- SEL.sub.-- CLRF, .sub.-- SEL.sub.-- DIAG, .sub.-- SEL.sub.--          EID, .sub.-- SEL.sub.-- KEY, .sub.-- SEL.sub.-- POST,                         .sub.-- SEL.sub.-- RTC,                                                    305.                                                                             .sub.-- TEST1, .sub.-- TEST2, .sub.-- XREADA, .sub.-- XREADB, .sub.--         XWRITE);                                                                   306.                                                                             input AEN, CS.sub.-- IN, FORCE.sub.-- XRA, FORCE.sub.-- XW, IOR, IOW,         RESET, SECURE;                                                             307.                                                                             output .sub.-- D.sub.-- OE, .sub.-- IO16, PRIVY, .sub.-- SEL.sub.--           CLRF, .sub.-- SEL.sub.-- DIAG, .sub.-- SEL.sub.-- EID, .sub.--                SEL.sub.-- KEY,                                                            308.                                                                             .sub.-- SEL.sub.-- POST, .sub.-- SEL.sub.-- RTC, .sub.-- TEST1,               .sub.-- TEST2, .sub.-- XREADA, .sub.-- XREADB, .sub.-- XWRITE;             309.                                                                             input [5:0] IRQ.sub.-- IN;                                                 310.                                                                             input [7:0] D.sub.-- IN;                                                   311.                                                                             input [2:0] DRQ.sub.-- IN;                                                 312.                                                                             input [5:0] DACK.sub.-- IN;                                                313.                                                                             input [15:0] ADD;                                                          314.                                                                             output [5:0] .sub.-- IRQ.sub.-- OUT;                                       315.                                                                             output [15:0] .sub.-- IO.sub.-- SEL;                                       316.                                                                             output [5:0] .sub.-- DRQ.sub.-- EN;                                        317.                                                                             output [2:0] .sub.-- DACK.sub.-- OUT;                                      318.                                                                             output [7:0] D.sub.-- OUT;                                                 319.                                                                             output [5:0] DRQ.sub.-- OUT;                                               320.                                                                             wire [5:0] FIXDIS;                                                         321.                                                                             wire [15:0] IX.sub.-- DEC;                                                 322.                                                                             wire [7:0] SEL0CMD;                                                        323.                                                                             wire [7:0] SEL1CMD;                                                        324.                                                                             wire [7:0] SEL2CMD;                                                        325.                                                                             wire [7:0] SEL3CMD;                                                        326.                                                                             wire [7:0] SEL4CMD;                                                        327.                                                                             wire [7:0] SEL6CMD;                                                        328.                                                                             wire [7:0] SEL7CMD;                                                        329.                                                                             wire [7:0] SEL8CMD;                                                        330.                                                                             wire [7:0] SEL9CMD;                                                        331.                                                                             wire [7:0] SEL10CMD;                                                       332.                                                                             wire [7:0] SEL11CMD                                                        333.                                                                             wire [7:0] SEL12CMD;                                                       334.                                                                             wire [7:0] SEL13CMD;                                                       335.                                                                             wire [7:0] SEL14CMD;                                                       336.                                                                             wire [7:0] SEL15CMD;                                                       337.                                                                             wire [7:0] SEL0MASK:                                                       338.                                                                             wire [7:0] SEL1MASK:                                                       339.                                                                             wire [7:0] SEL2MASK:                                                       340.                                                                             wire [7:0] SEL3MASK:                                                       341.                                                                             wire [7:0] SEL4MASK:                                                       342.                                                                             wire [7:0] SEL5MASK:                                                       343.                                                                             wire [7:0] SEL6MASK:                                                       344.                                                                             wire [7:0] SEL7MASK:                                                       345.                                                                             wire [7:0] SEL8MASK:                                                       346.                                                                             wire [7:0] SEL9MASK:                                                       347.                                                                             wire [7:0] SEL10MASK:                                                      348.                                                                             wire [7:0] SEL11MASK:                                                      349.                                                                             wire [7:0] SEL12MASK:                                                      350.                                                                             wire [7:0] SEL13MASK:                                                      351.                                                                             wire [7:0] SEL14MASK:                                                      352.                                                                             wire [7:0] SEL15MASK:                                                      353.                                                                             wire [7:0] SEL0UADD;                                                       354.                                                                             wire [7:0] SEL1UADD;                                                       355.                                                                             wire [7:0] SEL2UADD;                                                       356.                                                                             wire [7:0] SEL3UADD;                                                       357.                                                                             wire [7:0] SEL4UADD;                                                       358.                                                                             wire [7:0] SEL5UADD;                                                       359.                                                                             wire [7:0] SEL6UADD.                                                       360.                                                                             wire [7:0] SEL7UADD;                                                       361.                                                                             wire [7:0] SEL8UADD;                                                       362.                                                                             wire [7:0] SEL9UADD;                                                       363.                                                                             wire [7:0] SEL10UADD;                                                      364,                                                                             wire [7:0] SEL11UADD;                                                      365.                                                                             wire [7:0] SEL12UADD;                                                      366.                                                                             wire [7:0] SEL13UADD;                                                      367.                                                                             wire [7:0] SEL14UADD;                                                      368.                                                                             wire [7:0] SEL15UADD;                                                      369.                                                                             wire [7:0] SEL0LADD;                                                       370.                                                                             wire [7:0] SEL1IADD;                                                       371.                                                                             wire [7:0] SE12LADD;                                                       372.                                                                             wire [7:0] SEL3LADD;                                                       373.                                                                             wire [7:0] SEL4LADD;                                                       374.                                                                             wire [7:0] SEL5LADD;                                                       375.                                                                             wire [7:0] SEL6LADD;                                                       376.                                                                             wire [7:0] SEL7LADD;                                                       377.                                                                             wire [7:0] SEL8LADD;                                                       378.                                                                             wire [7:0] SEL9LADD;                                                       379.                                                                             wire [7:0] SEL10LADD;                                                      380.                                                                             wire [7:0] SEL11LADD;                                                      381.                                                                             wire [7:0] SEL12LADD;                                                      382.                                                                             wire [7:0] SEL13LADD;                                                      383.                                                                             wire [7:0] SEL14LADD;                                                      384.                                                                             wire [7:0] SEL15LADD;                                                      385.                                                                             wire [7:0] SEL5CMD;                                                        386.                                                                             wire [7:0] DMASW10;                                                        387.                                                                             wire [7:0] DMASW32;                                                        388.                                                                             wire [7:0] DMASW54;                                                        389.                                                                             wire [0:0] REGCNT;                                                         390.                                                                             wire [1:0] DMAX;                                                           391.                                                                             wire [7:0] IRQSEC;                                                         392.                                                                             wire [15:0] IO16.sub.-- SEL;                                               393.                                                                             wire [2:0] X14;                                                            394.                                                                             wire [2:0] X13;                                                            395.                                                                             wire [2:0] X12;                                                            396.                                                                             wire [2:0] X11;                                                            397.                                                                             wire [2:0] X10;                                                            398.                                                                             wire [2:0] X9;                                                             399.                                                                             wire [2:0] X8;                                                             400.                                                                             wire [2:0] X7;                                                             401.                                                                             wire [2:0] X6;                                                             402.                                                                             wire [2:0] X5;                                                             403.                                                                             wire [2:0] X4;                                                             404.                                                                             wire [2:0] X3;                                                             405.                                                                             wire [2:0] X2;                                                             406.                                                                             wire [2:0] X1;                                                             407.                                                                             wire [2:0] X0;                                                             408.                                                                             wire [2:0] X15;                                                            409.                                                                             wire [0:2] FXDEC;                                                          410.                                                                             wire [5:0] IRQO;                                                           411.                                                                             wire [7:0] IRQSW54;                                                        412.                                                                             wire [7:0] IRQSW32;                                                        413.                                                                             wire [7:0] IRQSW10;                                                        414.                                                                             wire [5:0] DRQ.sub.-- EN;                                                  415.                                                                             wire [2:0] ACK.sub.-- OUT;                                                 416.                                                                             wire [15:0] IO.sub.-- SEL;                                                 417.                                                                             wire [6:0] INDEX;                                                          418.                                                                             wire [5:0] .sub.-- IRQ.sub.-- OUT;                                         419.                                                                             wire [15:0] IO.sub.-- SEL;                                                 420.                                                                             wire [5:0] DRQ.sub.-- EN;                                                  421.                                                                             wire [2:0] .sub.-- DACK.sub.-- OUT;                                        422.                                                                             wire [7:0] D.sub.-- OUT;                                                   423.                                                                             wire [5:0] DRQ.sub.-- OUT;                                                 424.                                                                             wire [5:0] IRQ.sub.-- IN;                                                  425.                                                                             wire [7:0] D.sub.-- IN;                                                    426.                                                                             wire [2:0] DRQ.sub.-- IN;                                                  427.                                                                             wire [5:0] DACK.sub.-- IN;                                                 428.                                                                             wire [15:0] ADD;                                                           429.                                                                             dma.sub.-- sw I.sub.-- 23 (.DACK.sub.-- IN(DACK.sub.-- IN[5:0]),.DMASW1       0(DMASW10[7:0]),                                                           430.                                                                              .DMASW32(DMASW32[7:0]),.DMASW54(DMASW54[7:0]),                            431.                                                                              .DRQ.sub.-- IN(DRQ.sub.-- IN[2:0]),.IOR(IOR),.IOW(IOW),.PROG(PROG),       432.                                                                              .DACK.sub.-- OUT(ACK.sub.-- OUT[2:0]),.DRQ.sub.-- EN(DRQ.sub.--              EN[5:0]),                                                                  433.                                                                              .DRQ.sub.-- OUT(DRQ.sub.-- OUT[5:0]),.XA.sub.-- SEL(DMAX[0]),.XB.sub.-       - SEL(DMAX[1]));                                                           434.                                                                             iosel CS15 (.ADDRESS(ADD[15:0]),.AEN(AEN),.CMD.sub.-- REG(SEL15CMD[7:0]       ),                                                                         435.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),.IOR(IOR),.IOW(IOW),.I.sub.--              MTCH(IX.sub.-- DEC[15]),                                                   436.                                                                              .LADD.sub.-- REG(SEL15LADD[7:0]),.MASK.sub.-- REG(SEL15MASK[7:0]),        437.                                                                              .PRIVY(PRIVY),.PROG(PROG),.SECURE(SECURE),                                438.                                                                              .UADD.sub.-- REG(SEL15UADD[7:0]),.IGNORE.sub.-- RD(X15[2]),.IO16(IO16.       sub.-- SEL[15]),                                                           439.                                                                              .IO.sub.-- SEL(IO.sub.-- SEL[15]),.XA.sub.-- SEL(X15[0]),.XB.sub.--          SEL(X15[1]));                                                              440.                                                                             iosel CS14(.ADDRESS(ADD[15:0]),.AEN(AEN),.CMD.sub.-- REG(SEL14CMD[7:0])       ;                                                                          441.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),.IOR(IOR),.IOW(IOW),.I.sub.--              MTCH(IX.sub.-- DEC[14]),                                                   442.                                                                              .LADD.sub.-- REG(SEL14LADD[7:0]),.MASK.sub.-- REG(SEL14MASK[7:0]),        443.                                                                              .PRIVY(PRIVY),.PROG(PROG),.SECURE(SECURE),                                444.                                                                              .UADD.sub.-- REG(SEL14UADD [7:0]),.IGNORE.sub.-- RD(X14[2]),.IO16(IO16       .sub.-- SEL[14]),                                                          445.                                                                              IO.sub.-- SEL(IO.sub.-- SEL[14]),.XA.sub.-- SEL(X14[0]),.XB.sub.--           SEL(X14[1]));                                                              446.                                                                             iosel CS13(.ADDRESS(ADD[15:0]),.AEN(AEN),.CMD.sub.-- REG(SEL13CMD[7:0])       ,                                                                          447.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),.IOR(IOR),.IOW(IOW),.I.sub.--              MTCH(IX.sub.-- DEC[13]),                                                   448.                                                                              .LADD.sub.-- REG(SEL13LADD[7:0]),.MASK.sub.-- REG(SEL13MASK[7:0]),        449.                                                                              .PRIVY(PRIVY),.PROG(PROG),.SECURE(SECURE),                                450.                                                                              .UADD.sub.-- REG(SEL13UADD[7:0]),.IGNORE.sub.-- RD(X13[2]),.IO16(IO16.       sub.-- SEL[13]),                                                           451.                                                                              .IO.sub.-- SEL(IO.sub.-- SEL[13]),.XA.sub.-- SEL(X13[0]),.XB.sub.--          SEL(X13[1]));                                                              452.                                                                             iosel CS12(.ADDRESS(ADD[15:0]),.AEN(AEN),.CMD.sub.-- REG(SEL12CMD[7:0])       ,                                                                          453.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),.IOR(IOR),.IOW(IOW),.I.sub.--              MTCH(IX.sub.-- DEC[12]),                                                   454.                                                                              .LADD.sub.-- REG(SEL12LADD[7:0]),.MASK.sub.-- REG(SEL12MASK[7:0]),        455.                                                                              .PRIVY(PRIVY),.PROG(PROG),.SECURE(SECURE),                                456.                                                                              .UADD.sub.-- REG(SEL12UADD[7:0]),.IGNORE.sub.-- RD(X12[2]),.IO16(1016.       sub.-- SEL[12]),                                                           457.                                                                              .IO.sub.-- SEL(IO.sub.-- SEL[12]),.XA.sub.-- SEL(X12[0]),.XB.sub.--          SEL(X12[1]));                                                              458.                                                                             ioseI CS11(.ADDRESS(ADD[15:0]),.AEN(AEN),.CMD.sub.-- REG(SEL11CMD[7:0])       ,                                                                          459.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),.IOR(IOR),.IOW(IOW),.I.sub.--              MTCH(IX.sub.-- DEC[11]),                                                   460.                                                                              .LADD.sub.-- REG(SEL11LADD[7:0]),.MASK.sub.-- REG(SEL11MASK[7:0]),        461.                                                                              .PRIVY(PRIVY),.PROG(PROG),.SECURE(SECURE),                                462.                                                                              .UADD.sub.-- REG(SEL11UADD[7:0]),.IGNORE.sub.-- RD(X11[2]),.IO16(IO16.       sub.-- SEL[11]),                                                           463.                                                                              IO.sub.-- SEL(IO.sub.-- SEL[11]),.XA.sub.-- SEL(X11[0]),.XB.sub.--           SEL(X11[1]));                                                              464.                                                                             iosel CS10 (.ADDRESS(ADD[15:0]),.AEN(AEN),.CMD.sub.-- REG(SEL10CMD[7:0]       ),                                                                         465.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),.IOR(IOR),.IOW(IOW),.I.sub.--              MTCH(IX.sub.-- DEC[10]),                                                   466.                                                                              .LADD.sub.-- REG(SEL10LADD[7:0]),.MASK.sub.-- REG(SEL10MASK[7:0]),        467.                                                                              .PRIVY(PRIVY),.PROG(PROG),.SECURE(SECURE),                                468.                                                                              .UADD.sub.-- REG(SEL10UADD[7:0]),.IGNORE.sub.-- RD(X10[2]),.IO16(IO16.       sub.-- SEL[10]),                                                           469.                                                                              .IO.sub.-- SEL(IO.sub.-- SEL[10]),.XA.sub.-- SEL(X10[0]),.XB.sub.--          SEL(X10[1]));                                                              470.                                                                             iosel CS9(.ADDRESS(ADD[15:0]),.AEN(AEN),.CMD.sub.-- REG(SEL9CMD[7:0]),     471.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),.IOR(IOR),.IOW(IOW),.I.sub.--              MTCH(IX.sub.-- DEC[9]),                                                    472.                                                                              .LADD.sub.-- REG(SEL9LADD[7:0]),.MASK.sub.-- REG(SEL9MASK[7:0]),.PRIVY       (PRIVY),                                                                   473.                                                                              PROG(PROG),.SECURE(SECURE),.UADD.sub.-- REG(SEL9UADD[7:0]),               474.                                                                              .IGNORE.sub.-- RD(X9[2]),.IO16(IO16.sub.-- SEL[9]),.IO.sub.--                SEL(IO.sub.-- SEL[9]),                                                     475.                                                                              .XA.sub.-- SEL(X9[0]),.XB.sub.-- SEL(X9[1]));                             476.                                                                             iosel CSS(.ADDRSSS(ADD[15:0]),.AEN(AEN),.CMD.sub.-- REG(SEL8CMD[7:0]),     477.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),.IOR(IOR),.IOW(1OW),.I.sub.--              MTCH(IX.sub.-- DEC[8]),                                                    478.                                                                              .LADD.sub.-- REG(SEL8LADD[7:0]),.MASK.sub.-- REG(SEL8MASK[7:0]),.PRIVY       (PRIVY),                                                                   479.                                                                              .PROG(PROG),.SECURE(SECURE),.UADDREG(SEL8LADD[7:0]),                      480.                                                                              .IGNORE.sub.-- RD(X8[2]),.IO16(IO16.sub.-- SEL[8]),.IO.sub.--                SEL(IO.sub.-- SEL[8]),                                                     481.                                                                              .XA.sub.-- SEL(X8[0]),.XB.sub.-- SEL(X8[1]));                             482.                                                                             iosel CS7(.ADDRESS(ADD[15:0]), AEN(AEN),.CMD.sub.-- REG(SEL7CMD[7:0]),     483.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),.IOR(IOR),.IOW(IOW),.I.sub.--              MTCH(1X.sub.-- DEC[7]),                                                    484.                                                                              .LADD.sub.-- REG(SEL7LADD[7:0]),.MASK.sub.-- REG(SEL7MASK[7:0]),.PRIVY       (PRIVY),                                                                   485.                                                                              .PROG(PROG),.SECURE(SECURE),.UADD.sub.-- REG(SEL.sub.-- ADD[7:0]),        486.                                                                              .IGNORE.sub.-- RD(X7[2]),.IO16(IO16.sub.-- SEL[7]),.IO.sub.--                SEL(IO.sub.-- SEL[7]),                                                     487.                                                                              .XA.sub.-- SEL(X7[0]),.XB.sub.-- SEL(X7[1]));                             488.                                                                             iosel CS6(,ADDRESS(ADD[15:0]),.AEN(AEN),.CMD.sub.-- REG(SEL6CMD[7:0]),     489.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),.IOR(IOR),.IOW(IOW),.I.sub.--              MTCH(IX.sub.-- DEC[6]),                                                    490.                                                                              .LADD.sub.-- REG(SEL6LADD[7:0]),.MASK.sub.-- REG(SELSMASK[7:0]),.PRIVY       (PRIVY),                                                                   491.                                                                              .PROG(PROG),.SECURE(SECURE),.UADD.sub.-- REG(SEL6UADD[7:0]),              492.                                                                              .IGNORE.sub.-- RD(X6[2]),.IO16(IO16.sub.-- SEL[6]),.IO.sub.--                SEL(IO.sub.-- SEL[6]),                                                     493.                                                                              .XA.sub.-- SEL(X6[0]),.XB.sub.-- SEL(X6[1]));                             494.                                                                             iosel CS5(.ADDRESS(ADD[15:0]),.AEN(AEN),.CMD.sub.-- REG(SEL5CMD[7:0]),     495.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),.IOR(IOR),.IOW(IOW),.I.sub.--              MTCH(IX.sub.-- DEC[5]),                                                    496.                                                                              .LADD.sub.-- REG(SEL5LADD[7:0]),.MASK.sub.-- REG(SEL5MASK[7:0]),.PRIVY       (PRIVY),                                                                   497.                                                                              .PROG(PROG),.SECURE(SECURE),.UADD.sub.-- REG(SEL5LADD[7:0]),              498.                                                                              .IGNORE.sub.-- RD(X5[2]),.IO16(IO16.sub.-- SEL[5]),.IO.sub.--                SEL(IO.sub.-- SEL[5]),                                                     499.                                                                              .XA.sub.-- SEL(X5[0]),.XB.sub.-- SEL(X5[1]));                             500.                                                                             iosel CS4(.ADDRESS(ADD[15:0]),.AEN(AEN),.CMD.sub.-- REG(SEL4CMD[7:0]),     501.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),.IOR(IOR),.IOW(IOW),.I.sub.--              MTCH(IX.sub.-- DEC[4]),                                                    502.                                                                              .LADD.sub.-- REG(SEL4LADD[7:0]),.MASK.sub.-- REG(SEL4MASK[7:0]),.PRIVY       (PRIVY),                                                                   503.                                                                              .PROG(PROG),.SECURE(SECURE),.UADD.sub.-- REG(SEL4UADD[7:0]),              504.                                                                              .IGNORE.sub.-- RD(X4[2]),.IO16(IO16.sub.-- SEL[4]),.IO.sub.--                SEL(IO.sub.-- SEL[4]),                                                     505.                                                                              .XA.sub.-- SEL(X4[0]),.XB.sub.-- SEL(X4[1]));                             506.                                                                             iosel CS3(.ADDRESS(ADD[15:0]),.AEN(AEN),.CMD.sub.-- REG(SEL3CMD[7:0]),     507.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),.OOR(IOR),.IOW(IOW),.I.sub.--              MTCH(IX.sub.-- DEC[3]),                                                    508.                                                                              .LADD.sub.-- REG(SEL)LADD[7:0]),.MASK.sub.-- REG(SEL3MASK[7:0]),.PRIVY       (PRIVY),                                                                   509.                                                                              .PROG(PROG),.SECURE(SECURE),.UADDREG(SEL3UADD[7:0]),                      510.                                                                              .IGNORE.sub.-- RD(X)[2]),.IO16(IO16.sub.-- SEL[3]),.IO.sub.--                SEL(IO.sub.-- SEL[3]),                                                     511.                                                                              .XA.sub.-- SEL(X3[0]),.XB.sub.-- SEL(X3[1]));                             512.                                                                             iosel CS2(.ADDRESS(ADD[15:0]),.AEN(AEN),.CMD.sub.-- REG(SEL2CMD[7:0]),     513.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),.IOR(IOR),.IOW(IOW),.I.sub.--              MTCH(IX.sub.-- DEC[2]),                                                    514.                                                                              .LADD.sub.-- REG(SEL2LADD[7:0]),.MASK.sub.-- REG(SEL2MASK[7:0]),.PRIVY       (PRIVY),                                                                   515.                                                                              .PROG(PROG),.SECURE(SECURE),.UADD.sub.-- REG(SEL2UADD[7:0]),              516.                                                                              .IGNORE.sub.-- RD(X2[2]),.IO16(IO16.sub.-- SEL[2]),.IO.sub.--                SEL(IO.sub.-- SEL[2]),                                                     517.                                                                              .XA.sub.-- SEL(X2[0]),.XB.sub.-- SEL(X2[1]));                             518.                                                                             iosel CS1(.ADDRESS(ADD[15:0]),.AEN(AEN),.CMD.sub.-- REG(SEL1CMD[7:0]),     519.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),,IOR(IOR),.IOW(IOW),.I.sub.--              MTCH(IX.sub.-- DEC[1]),                                                    520.                                                                              .LADD.sub.-- REG(SEL1LADD[7:0]),.MASK.sub.-- REG(SEL1MASK[7:0]),.PRIVY       (PRIVY),                                                                   521.                                                                              .PROG(PROG),.SECURE(SECURE),.UADD.sub.-- REG(SEL1UADD[7:0]),              522.                                                                              IGNORE.sub.-- RD(X1[2]),.IO16(IO16.sub.-- SEL[1]),.IO.sub.-- SEL(IO.su       b.-- SEL[1]),                                                              523.                                                                              .XA.sub.-- SEL(X1[0]),.XB.sub.-- SEL(X1[1]));                             524.                                                                             iosel CS0(.ADDRESS(ADD[15:0]),.AEN(AEN),.CMD.sub.-- REG(SEL0CMD[7:0]),     525.                                                                              .DATA.sub.-- DEC(DATA.sub.-- DEC),.IOR(IOR),.IOW(IOW),.I.sub.--              MTCH(1X.sub.-- DEC[0]),                                                    526.                                                                              .LADD.sub.-- REG(SEL0LADD[7:0]),.MASK.sub.-- REG(SEL0MASK[7:0]),.PRIVY       (PRIVY),                                                                   527.                                                                              .PROG(PROG),.SECURE(SECURE),.UADD.sub.-- REG(SEL0UADD[7:0]),              528.                                                                              .IGNQRE.sub.-- RD(X0[2]),.IO16(IO16.sub.-- SEL[0]),.IO.sub.--                SEL(IO.sub.-- SEL[0]),                                                     529.                                                                              .XA.sub.-- SEL(X0[0]),.XB.sub.-- SEL(X0[1]));                             530.                                                                             irqswch IRQSWCH(.DIS0(IRQSW10[3]),.DIS1(IRQSW10[7]),                       531.                                                                              .DIS2(IRQSW32[3]),.DIS3(IRQSW32[7]),..DIS4(IRQSW54[3]),                   532.                                                                              .DIS5(IRQSW54[7]),.PROG(PROG),.REQ.sub.-- IN(IRQ.sub.-- IN[5:0]),         533.                                                                              .SEC0(IRQSEC[0]),.SEC1(IRQSEC[1]), SEC2(IRQSEC[2]),                       534.                                                                              .SEC3(IRQSEC[3]),.SEC4(IRQSEC[4]),.SEC5(IRQSEC[5]),                       535.                                                                              .SECURE(SECURE),.SEL0(IRQSW10[2:0]),.SELI(IRQSW10[6:4]),                  536.                                                                              .SEL2(IRQSW32[2:0]),.SEL3(IRQSW32[6:4]),.SEL4(IRQSW54[2:0]),              537.                                                                              .SEL5(IRQSW54[6:4]),.REQ.sub.-- OUT(IRQO[5:0]));                          538.                                                                             xbus.sub.-- cnt XBUSCNT(.CS.sub.-- IN(CS.sub.-- IN),.DLY.sub.--               SEL(IRQSEC[7:6]),                                                          539.                                                                              .DMAX(DMAX[1:0]),.FORCE.sub.-- XRA(FORCE.sub.-- XRA),.FORCE.sub.--           XW(FORCE.sub.-- XW),                                                       540.                                                                              .FXDEC0(FXDEC[0]),.FXDEC2(FXDEC[2]),.IO16.sub.-- IN(IO16.sub.--              SEL[15:0]),                                                                541.                                                                              .IOR(IOR),.IOW(IOW),.REGCNT0)(REGCNT[0]),.X0(X0[2:0]),                    542.                                                                              .X10(X10[2:0]),.X11(X11[2:0]),.X12(X12[2:0]),.X13(X13[2:0]),              543.                                                                              .X14(X14[2:0]),.X15(X15[2:0]),.X1(X1[2:0]),.X2(X2[2:0]),                  544.                                                                              .X3(X3[2:0]),.X4(X4[2:0]),.X5(X5[2:0]),.X6(X6[2:0]),                      545.                                                                              .X7(X7[2:0]),.X8(X8[2:0]),.X9(X9[2:0]),.IO16(N.sub.-- 1),.XREADA(N.sub       .-- 3),                                                                    546.                                                                              .XREADB(N.sub.-- 4),.XWRITE(N.sub.-- 2));                                 547.                                                                             fix.sub.-- deco FIXDEC(.ADD(ADD[15:0]),.AEN(AEN),.DISABLE(FIXDIS[5.0]),    548.                                                                             .IOR(IOR),.IOW(IOW),.RESET(RESET),.IGNORE.sub.-- RD(FXDEC[2]),             549,                                                                             .PRIVY(PRIVY),.SEL.sub.-- CLRF(SEL#CLRF),.SEL.sub.-- DIAG(SEL#DIAG),       550.                                                                             .SEL.sub.-- EID(SEL.sub.-- EID),.SEL.sub.-- KEY(SEL.sub.-- KEY),.SEL.su       b.-- POST(SEL.sub.-- POST),                                                551.                                                                             .SEL.sub.-- RTC(SEL.sub.-- RTC),.XA.sub.-- SEL(FXDEC[0]));                 552.                                                                             nand I.sub.-- 37 (.sub.-- TEST1, IOR, IOW);                                553.                                                                             nand I.sub.-- 40 (.sub.-- TEST2, IOR, IOW);                                554.                                                                             regcntrl REGCNTRL(.ADDRESS(ADD[15:0]),.AEN(AEN),.D.sub.-- IN(D.sub.--         IN[7:0]),                                                                  555.                                                                              IOR(IOR),.IOW(IOW),.PRIVY(PRIVY),.RESET(RESET),                           556.                                                                              .SECURE(SECURE),.DATA.sub.-- DEC(DATA.sub.-- DEC),.DMASW10(DMASW10[7:0       ]),                                                                        557.                                                                              .DMASW32(DMASW32[7:0]),.DMASW54(DMASW54[7:0]),.D.sub.-- OUT(D.sub.--         OUT[7:0]),                                                                 558.                                                                              .FIXDIS(FIXDIS[5:0]),.INDEX(INDEX[6:0]),.IRQSEC(IRQSEC[7:0]),             559.                                                                              .IRQSW10(IRQSW10[7:0]),.IRQSW32(IRQSW32[7:0]),                            560.                                                                              .IRQSW54(IRQSW54[7:0]),.OUT.sub.-- EN(D.sub.-- OE),.PROG(PROG),           561.                                                                              .SEL0CMD(SEL0CMD[7:0]),.SEL0LADD(SEL0LADD[7:0]),                          562.                                                                              .SEL0MASK(SEL0MASK[7:0]),.SEL0UADD(SEL0UADD[7:0]),                        563.                                                                              .SEL10CMD(SEL10CMD[7:0]),.SEL10LADD(SEL10LADD[7:0]),                      564.                                                                              .SEL10MASK(SEL10MASK[7:0]),.SEL10UADD(SEL10UADD[7:0]),                    565.                                                                              .SEL11CMD(SEL11CMD[7:0]),.SEL11LADD(SEL11LADD[7:0]),                      566.                                                                              .SEL11MASK(SEL11MASK[7:0]),.SEL11UADD(SEL11UADD[7:0]),                    567.                                                                              .SEL12CMD(SEL12CMD[7:0]),.SEL12LADD(SEL12LADD[7:0]),                      568.                                                                              .SEL12MASK(SEL12MASK[7:0]),.SEL12UADD(SEL12UADD[7:0]),                    569.                                                                              .SEL13CMD(SEL13CMD[7:0]),.SEL13LADD(SEL13LADD[7:0]),                      570.                                                                              .SEL13MASK(SEL13MASK[7:0]),.SEL13UADD(SEL13UADD[7:0]),                    571.                                                                              .SEL14CMD(SEL14CMD[7:0]),.SEL14LADD(SEL14LADD[7:0]),                      572.                                                                              .SEL14MASK(SEL14MASK[7:0]),.SEL14UADD(SEL14UADD[7:0]),                    573.                                                                              .SEL15CMD(SEL15CMD[7:0]),.SEL15LADD(SEL15LADD[7:0]),                      574.                                                                              .SEL15MASK(SEL15MASK[7:0]),.SEL15UADD(SEL15UADD[7:0]),                    575.                                                                              .SEL1CMD(SEL1CMD[7:0]),.SEL1LADD(SEL1LADD[7:0]),                          576.                                                                              .SEL1MASK(SEL1MASK[7:0]),.SEL1UADD(SEL1UADD[7:0]),.                       577.                                                                              .SEL2CMD(SEL2CMD[7:0]),.SEL2LADD(SEL2LADD[7:0]),                          578.                                                                              .SEL2MASK(SEL2MASK[7:0]),.SEL2UADD(SEL2UADD[7:0]),                        579.                                                                              .SEL3CMD(SEL3CMD[7:0]),.SEL3LADD(SEL3LADD[7:0]),                          580.                                                                              .SEL3MASK(SEL3MASK[7:0]),.SEL3UADD(SEL3UADD[7:0]),                        581.                                                                              .SEL4CMD(SEL4CMD[7:0]),.SEL4LADD(SEL4LADD[7:0]),                          582.                                                                              .SEL4MASK(SEL4MASK[7:0]),.SEL4UADD(SEL4UADD[7:0]),                        583.                                                                              .SEL5CMD(SEL5CMD[7:0]),.SEL5LADD(SEL5LADD[7:0]),                          584.                                                                              .SEL5MASK(SEL5MASK[7:0]),.SEL5UADD(SEL5UADD[7:0]),                        585.                                                                              .SEL6CMD(SEL6CMD[7:0]),.SEL6LADD(SEL6LADD[7:0]),                          586.                                                                              .SEL6MASK(SEL6MASK[7:0]),.SEL6UADD(SEL6UADD[7:0]),                        587.                                                                              .SEL7CMD(SEL7CMD[7:0]),.SEL7LADD(SEL7LADD[7:0]),                          588.                                                                              .SEL7MASK(SEL7MASK[7:0]),.SEL7UADD(SEL7UADD[7:0]),                        589.                                                                              .SEL8CMD(SEL8CMD[7:0]),.SEL8LADD(SEL8LADD[7:0]),                          590.                                                                              .SEL8MASK(SEL8MASK[7:0]),.SEL8UADD(SEL8UADD[7:0]),                        591.                                                                              .SEL9CMD(SEL9CMD[7:0]),.SEL9LADD(SEL9LADD[7.0]),                          592.                                                                              .SEL9MASK(SEL9MASK[7:0]),.SEL9UADD(SEL9UADD[7:0]),                        593.                                                                              .XA.sub.-- SEL(REGCNT[0]));                                               594.                                                                             ix.sub.-- deco I.sub.-- 22(.INDEX(INDEX[6:0]),.IX.sub.-- DECODE(IX.sub.       -- DEC[15:0]));                                                            595.                                                                             not \IOS[15](.sub.-- IO.sub.-- SEL[15], IO.sub.-- SEL[15]);      596.                                                                             not \IOS[14](.sub.-- IO.sub.-- SEL[14], IO.sub.-- SEL[14]);      597.                                                                             not \IOS[13](.sub.-- IO.sub.-- SEL[13], IO.sub.-- SEL[13]);      598.                                                                             not \IOS[12](.sub.-- IO.sub.-- SEL[12], IO.sub.-- SEL[12]);      599.                                                                             not \IOS[11](.sub.-- IO.sub.-- SEL[11], IO.sub.-- SEL[11]);      600.                                                                             not \IOS[10](.sub.-- IO.sub.-- SEL[10], IO.sub.-- SEL[10]);      601.                                                                             not \IOS[9](.sub.-- IO.sub.-- SEL[9], IO.sub.-- SEL[9]);         602.                                                                             not \IOS[8](.sub.-- IO.sub.-- SEL[8], IO.sub.-- SEL[8]);         603.                                                                             not \IOS[7](.sub.-- IO.sub.-- SEL[7], IO.sub.-- SEL[7]);         604.                                                                             not \IOS[6](.sub.-- IO.sub.-- SEL[6], IO.sub.-- SEL[6]);         605.                                                                             not \IOS[5](.sub.-- IO.sub.-- SEL[5], IO.sub.-- SEL[5]);         606.                                                                             not \IOS[4](.sub.-- IO.sub.-- SEL[4], IO.sub.-- SEL[4]);         607.                                                                             not \IOS[3](.sub.-- IO.sub.-- SEL[3], IO.sub.-- SEL[3]);         608.                                                                             not \IOS[2](.sub.-- IO.sub.-- SEL[2], IO.sub.-- SEL[2]);         609.                                                                             not \IOS[1](.sub.-- IO.sub.-- SEL[1], IO.sub.-- SEL[1]);         610.                                                                             not \IOS[0](.sub.-- IO.sub.-- SEL[0], IO.sub.-- SEL[0]);         611.                                                                             not \DAO[2](.sub.-- DACK.sub.-- OUT[2], ACK.sub.-- OUT[2]);      612.                                                                             not \DAO[1](.sub.-- DACK.sub.-- OUT[1], ACK.sub.-- OUT[1]);      613.                                                                             not \DAO[0](.sub.-- DACK.sub.-- OUT[0], ACK.sub.-- OUT[0]);      614.                                                                             not \DQE[5](.sub.-- DRQ.sub.-- EN[5], DRQ.sub.-- EN[5]);         615.                                                                             not \DQE[4](.sub.-- DRQ.sub.-- EN[4], DRQ.sub.-- EN[4]);         616.                                                                             not \DQE[3](.sub.-- DRQ.sub.-- EN[3], DRQ.sub.-- EN[3]);         617.                                                                             not \DQE[2](.sub.-- DRQ.sub.-- EN[2], DRQ.sub.-- EN[2]);         618.                                                                             not \DQE[1](.sub.-- DRQ.sub.-- EN[1], DRQ.sub.-- EN[1]);         619.                                                                             not \DQE[0](.sub.-- DRQ.sub.-- EN[0], DRQ.sub.-- EN[0]);         620.                                                                             not \IQO[5](.sub.-- IRQ.sub.-- OUT[5], IRQO[5]);                 621.                                                                             not \IQO[4](.sub.-- IRQ.sub.-- OUT[4], IRQO[4]);                 622.                                                                             not \IQO[3](.sub.-- IRQ.sub.-- OUT[3], IRQO[3]);                 623.                                                                             not \IQO[2](.sub.-- IRQ.sub.-- OUT[2], IRQO[2]);                 624.                                                                             not \IQO[1](.sub.-- IRQ.sub.-- OUT[1], IRQO[1]);                 625.                                                                             not \IQO[0](.sub.-- IRQ.sub.-- OUT[0], IRQO[0]);                 626.                                                                             not I.sub.-- 32(.sub.-- XREADB, N.sub.-- 4);                               627.                                                                             not I.sub.-- 33(.sub.-- XREADA, N.sub.-- 3);                               628.                                                                             not I.sub.-- 34(.sub.-- XWRITE, N.sub.-- 2);                               629.                                                                             not I.sub.-- 35(.sub.-- IO16, N.sub.-- 1);                                 630.                                                                             not I.sub.-- 25(.sub.-- SEL.sub.-- EID, SEL.sub.-- EID);                   631.                                                                             not I.sub.-- 26(.sub.-- SEL.sub.-- CLRF, SEL.sub.-- CLRF);                 632.                                                                             not I.sub.-- 27(.sub.-- SEL.sub.-- RTC, SEL.sub.-- RTC);                   633.                                                                             not I.sub.-- 28(.sub.-- SEL.sub.-- KEY, SEL.sub.-- KEY);                   634.                                                                             not I.sub.-- 29(.sub.-- PRIVY, PRIVY);                                     635.                                                                             not I.sub.-- 30(.sub.-- SEL.sub.-- DIAG, SEL.sub.-- DIAG);                 636.                                                                             not I.sub.-- 31(.sub.-- SEL.sub.-- POST, SEL.sub.-- POST);                 637.                                                                             not I.sub.-- 39(.sub.-- D.sub.-- OE, D.sub.-- OE);                         638.                                                                             endmodule // core                                                          639.                                                                             ///////////////////////////////////////////////////////////////////        640.                                                                             // MODULE: dma.sub.-- sw                                                   641.                                                                             // It also controlles the XBUS for use during ACK's and will tristate      642.                                                                             // use this line.                                                          643.                                                                             //                                                                         644.                                                                             // The XBUS control for the bus side ACKs ate programmable via bits        645.                                                                             // 3,2 and 7,6 in the DMASW registers                                      646.                                                                             //                                                                         647.                                                                             //      DMA.sub.-- ACK will control XBUS even when not enabled.            648.                                                                             //      will not be able to configure a DACK on both buses                 649.                                                                             //                                                                         650.                                                                             `define DMA.sub.-- SW.sub.-- REV 1.10                                      651.                                                                             //                                                                         652.                                                                             // DESCRIPTION: This block performs the mapping of 3 dma channels in          to                                                                         653.                                                                             // a single DMA channel in. Disabled DMA channcls out will still              control                                                                    654.                                                                             // the XBUS via DACK in.                                                   655.                                                                             module dma.sub.-- sw( DACK.sub.-- IN, DMASW10, DMASW32, DMASW54,              DRQ.sub.-- IN, IOR, IOW, PROG                                              656.                                                                             , DACK.sub.-- OUT, DRQ.sub.-- EN, DRQ.sub.-- OUT, XA.sub.-- SEL,              XB.sub.-- SEL);                                                            657.                                                                             input IOR, IOW, PROG;                                                      658.                                                                             output XA.sub.-- SEL, XB.sub.-- SEL;                                       659.                                                                             input [2:0] DRQ.sub.-- IN;                                                 660.                                                                             input [7:0] DMASW54;                                                       661.                                                                             input [7:0] DMASW32;                                                       662.                                                                             input [7:0] DMASW10;                                                       663.                                                                             input [5:0] DACK.sub.-- IN;                                                664.                                                                             output [5:9] DRQ.sub.-- OUT;                                               665.                                                                             output [5:0] DRQ.sub.-- EN;                                                666.                                                                             output [2:0] DACK.sub.-- OUT;                                              667.                                                                             // tristate enables for thc DRQ.sub.-- OUT pads. (disabled when not           assigned                                                                   668.                                                                             // to one of the input channels.)                                          669.                                                                             wire EN5=!PROG && DMASW54[5:4]!=2`b11;                                     670.                                                                             wire EN4=!PROG && DMASW54[1:0]!=2`b11;                                     671.                                                                             wire EN3=!PROG && DMASW32[5:4]!=2`b11;                                     672.                                                                             wire EN2=!PROG && DMASW32[1:0]!=2`b11;                                     673.                                                                             wire EN1=!PROG && DMASW10[5:4]!=2`b11;                                     674.                                                                             wire EN0=!PROG && DMASW10[1:0]!=2`b11;                                     675.                                                                             wire [5:0] DRQ.sub.-- EN = {EN5, EN4, EN3, EN2, EN1, EN0};                 676.                                                                             wire DRQ5 = EN5 && (DMASW54[5:4]==2`b00 && DRQ.sub.-- IN[0])                  ∥                                                                 677.                                                                               (DMASW54[5:4]==2`b01 && DRQ.sub.-- IN[1]) ∥                     678.                                                                               (DMASW54[5:4]==2`b10 && DRQ.sub.-- IN[2]);                               679.                                                                             wire DRQ4 = EN4 && (DMASW54[1:0]==2`b00 && DRQ.sub.-- IN[0])                  ∥                                                                 680.                                                                               (DMASW54[1:0]==2`b01 && DRQ.sub.-- IN[1]) ∥                     681.                                                                               (DMASW54[1:0]==2`b10 && DRQ.sub.-- IN[2]);                               682.                                                                             wire DRQ3 = EN3 && (DMASW32[5:4]==2`b00 && DRQ.sub.-- IN[0])                  ∥                                                                 683.                                                                               (DMASW32[5:4]==2`b01 && DRQ.sub.-- IN[1]) ∥                     684.                                                                               (DMASW32[5:4]==2`b10 && DRQ.sub.-- IN[2]);                               685.                                                                             wire DRQ2 = EN2 && (DMASW32[1:0]==2`b00 && DRQ.sub.-- IN[0])                  ∥                                                                 686.                                                                               (DMASW32[1:0]==2`b01 && DRQ.sub.-- IN[1]) ∥                     687.                                                                               (DMASW32[1:0]==2`b10 && DRQ.sub.-- IN[2]);                               688.                                                                             wire DRQ1 = EN1 && (DMASW10[5:4]==2`b00 && DRQ.sub.-- IN[0])                  ∥                                                                 689.                                                                               (DMASW10[5:4]==2`b01 && DRQ.sub.-- IN[1]) ∥                     690.                                                                               (DMASW10[5:4]==2`b10 && DRQ.sub.-- IN[2]);                               691.                                                                             wire DRQO = EN0 && (DMASW10[1:0]==2`b00 && DRQ.sub.-- IN[0])               692.                                                                               (DMASW10[1:0]==2`b01 && DRQ.sub.-- IN[1]) ∥                     693.                                                                               (DMASW10[1:0]==2`b10 && DRQ.sub.-- IN[2]);                               694.                                                                             wire [5:0] DRQ.sub.-- OUT = {DRQ5, DRQ4, DRQ3, DRQ2, DRQ1, DRQ0};          695.                                                                             wire DACKO = !PROG && (                                                    696.                                                                               (DMASW54[5:4]==2`b00 && DACK.sub.-- IN[5]) ∥                    697.                                                                               (DMASW54[1:0]==2`b00 && DACK.sub.-- IN[4]) ∥                    698.                                                                               (DMASW32[5:4]==2`b00 && DACK.sub.-- IN[3]) ∥                    699.                                                                               (DMASW32[1:0]==2`b00 && DACK.sub.-- IN[2]) ∥                    700.                                                                               (DMASW10[5:4]==2`b00 && DACK.sub.-- IN[1]) ∥                    701.                                                                               (DMASW10[1:0]==2`b00 && DACK.sub.-- IN[0]);                              702.                                                                             wire DACK1 = !PROG && (                                                    703.                                                                               (DMASW54[5:4]==2`b01 && DACK.sub.-- IN[5]) ∥                    704.                                                                               (DMASW54[1:0]==2`b01 && DACK.sub.-- IN[4]) ∥                    705.                                                                               (DMASW32[5:4]==2`b01 && DACK.sub.-- IN[3]) ∥                    706.                                                                               (DMASW32[1:0]==2`b01 && DACK.sub.-- IN[2]) ∥                    707.                                                                               (DMASW10[5:4]==2`b01 && DACK.sub.-- IN[1]) ∥                    708:                                                                               (DMASW10[1:0]==2`b01 && DACK.sub.-- IN[0]);                              709.                                                                             wire DACK2 = !PROG && (                                                    710.                                                                               (DMASW54[5:4]==2`b10 && DACK.sub.-- IN[5]) ∥                    711.                                                                               (DMASW54[1:0]==2`b10 && DACK.sub.-- IN[4]) ∥                    712.                                                                               (DMASW32[5:4]==2`b10 && DACK.sub.-- IN[3]) ∥                    713.                                                                               (DMASW32[1:0]==2`b10 && DACK.sub.-- IN[2]) ∥                    714.                                                                               (DMASW10[5:4]==2`b10 && DACK.sub.-- IN[1]) ∥                    715.                                                                               (DMASW10[1:0]==2`b10 && DACK.sub.-- IN[0]);                              716.                                                                             wire [2:0] DACK.sub.-- OUT = {DACK2, DACK1, DACK0};                        717.                                                                             // firmware will not be allowed to configure a DACK to use                 718.                                                                             // both xbuses.                                                            719.                                                                             wire XA5=DACK.sub.-- IN[5] && !DMASW54[7] && DMASW54[6] && !PROG;          720.                                                                             wire XA4=DACK.sub.-- IN[4] && !DMASW54[3] && DMASW54[2] && !PROG;          721.                                                                             wire XA3=DACK.sub.-- IN[3] && !DMASW32[7] && DMASW32[6] && !PROG;          722.                                                                             wire XA2=DACK.sub.-- IN[2] && !DMASW32[3] && DMASW32[2] && !PROG;          723.                                                                             wire XA1=DACK.sub.-- IN[1] && !DMASW10[7] && DMASW10[6] && !PROG;          724.                                                                             wire XA0=DACK.sub.-- IN[0] && !DMASW10[3] && DMASW10[2] && !PROG;          725.                                                                             wire XB5=DACK.sub.-- IN[5] && DMASW54[7] && !DMASW54[6] && !PROG;          726.                                                                             wire XB4=DACK.sub.-- IN[4] && DMASW54[3] && !DMASW54[2] && !PROG;          727.                                                                             wire XB3=DACK.sub.-- IN[3] && DMASW32[7] && !DMASW32[6] && !PROG;          728.                                                                             wire XB2=DACK.sub.-- IN[2] && DMASW32[3] && !DMASW32[2] && !PROG;          729.                                                                             wire XB1=DACK.sub.-- IN[1] && DMASW10[7] && !DMASW10[6] && !PROG;          730.                                                                             wire XB0=DACK.sub.-- IN[0] && DMASW10[3] && !DMASW10[2] && !PROG;          731.                                                                             wire XA.sub.-- SEL = (XA5 ∥ XA4 ∥ XA3 ∥ XA2        ∥ XA1 ∥ XA0);                                            732.                                                                             wire XB.sub.-- SEL = (XB5 ∥ XB4 ∥ XB3 ∥ XB2        ∥ XB1 ∥ XB0);                                            733.                                                                             endmodule // dma.sub.-- sw                                                 734.                                                                             `include "defines.h" // comments                                           735.                                                                             ///////////////////////////////////////////////////////////////////        736.                                                                             // MODULE:  FIX DECO                                                       737.                                                                             // MODIFICATIONS:                                                          738.                                                                             //                                                                         739.                                                                             `define FIX.sub.-- DEC.sub.-- REV 1.00                                     740.                                                                             //                                                                         741.                                                                             // DESCRIPTION:                                                            742.                                                                             // This module performs the decode of all fixed ports. It includes         743.                                                                             // decode of address and command information.                              744.                                                                             module fix.sub.-- deco( ADD, AEN, DISABLE, IOR, IOW, RESET,                   IGNORE.sub.-- RD, PRIVY,                                                   745.                                                                               SEL.sub.-- CLRF, SEL.sub.-- DIAG, SEL.sub.-- EID, SEL.sub.-- KEY,           SEL.sub.-- POST, SEL.sub.-- RTC, XA.sub.-- SEL);                           746.                                                                             input AEN, IOR, IOW, RESET;                                                747.                                                                             output IGNORE.sub.-- RD, PRIVY, SEL.sub.-- CLRF, SEL.sub.-- DIAG,             SEL.sub.-- EID, SEL.sub.-- KEY, SEL.sub.-- POST                            748.                                                                             , SEL.sub.-- RTC, XA.sub.-- SEL;                                           749.                                                                             input [5:0] DISABLE;                                                       750.                                                                             input [15:0] ADD;                                                          751.                                                                             wire PRIVY;                                                                752.                                                                             wire POST.sub.-- ADD.sub.-- MTCH = ADD==`POST && !AEN && !DISABLE[0];      753.                                                                             wire POST.sub.-- CMD.sub.-- MTCH = IOW;                                    754.                                                                             wire SEL.sub.-- POST = POST.sub.-- ADD.sub.-- MTCH && POST.sub.--             CMD.sub.-- MTCH;                                                           755.                                                                             wire POST.sub.-- XA.sub.-- SEL = POST.sub.-- ADD.sub.-- MTCH;              756.                                                                             wire DIAG.sub.-- ADD.sub.-- MTCH = ADD==`DIAG && !AEN && !DISABLE[1]          && PRIVY.                                                                  757.                                                                             wire DIAG.sub.-- CMD.sub.-- MTCH = IOW;                                    758.                                                                             wire SEL.sub.-- DIAG = DIAG.sub.-- ADD.sub.-- MTCH && DIAG.sub.--             CMD.sub.-- MTCH;                                                           759.                                                                             wire DIAG.sub.-- XA.sub.-- SEL = DIAG.sub.-- ADD.sub.-- MTCH;              760.                                                                             wire KEY.sub.-- ADD.sub.-- MTCH = (ADD==`KEY.sub.-- STATUS ∥         ADD==`KEY.sub.-- DATA) && !AEN && !DISABLE[2];                             761.                                                                             wire KEY.sub.-- CMD.sub.-- MTCH = 1;                                       762.                                                                             wire SEL.sub.-- KEY = KEY.sub.-- ADD.sub.-- MTCH && KEY.sub.--                CMD.sub.-- MTCH;                                                           763.                                                                             wire KEY.sub.-- XA.sub.-- SEL = KEY.sub.-- ADD.sub.-- MTCH;                764.                                                                             wire RTC.sub.-- ADD.sub.-- MTCH = (ADD==`RTC.sub.-- I ∥              ADD==`RTC.sub.-- D) && !AEN && !DISABLE[3];                                765.                                                                             wire RTC.sub.-- CMD.sub.-- MTCH =1;                                        766.                                                                             wire SEL.sub.-- RTC = RTC.sub.-- ADD.sub.-- MTCH && RTC.sub.--                CMD.sub.-- MTCH;                                                           767.                                                                             wire RTC.sub.-- XA.sub.-- SEL = RTC.sub.-- ADD.sub.-- MTCH;                768.                                                                             wire CLRF.sub.-- ADD.sub.-- MTCH = ADD==`CLRF && !AEN && !DISABLE[4];      769.                                                                             wire CLRF.sub.-- CMD.sub.-- MTCH = IOW;                                    770.                                                                             wire SEL.sub.-- CLRF = CLRF.sub.-- ADD.sub.-- MTCH && CLRF.sub.--             CMD.sub.-- MTCH;                                                           771.                                                                             wire EID.sub.-- ADD.sub.-- MTCH = (ADD | `EID.sub.-- MASK)==`E       ID && !AEN && !DISABLE[5];                                                 772.                                                                             wire EID.sub.-- CMD.sub.-- MTCH = IOR;                                     773.                                                                             wire SEL.sub.-- EID = EID.sub.-- ADD.sub.-- MTCH && EID.sub.--                CMD.sub.-- MTCH;                                                           774.                                                                             wire EID.sub.-- XA.sub.-- SEL = EID.sub.-- ADD.sub.-- MTCH;                775.                                                                             // all fixed registers are hard coded on the XBUSA                         776.                                                                             wire XA.sub.-- SEL = POST.sub.-- XA.sub.-- SEL ∥ DIAG.sub.--         XA.sub.-- SEL ∥ KEY.sub.-- XA.sub.-- SEL ∥ RTC.sub.--        XA.sub.-- SEL ∥ EID.sub.-- XA.sub.-- SEL;                        777.                                                                             wire IGNORE.sub.-- RD = POST.sub.-- XA.sub.-- SEL ∥ DIAG.sub.-       - XA.sub.-- SEL;                                                           778.                                                                             wire privy.sub.-- gate = !AEN && IOW && (ADD==`PRIVY.sub.-- ON                ∥ ADD==`PRIVY.sub.-- OFF);                                        779.                                                                             wire privy.sub.-- on = !AEN && (ADD==`PRIVY OFF);                          780.                                                                             LD3 PRIV (.D(privy.sub.-- on),.G(privy.sub.-- gate),.CD(!RESET),.QN(PRI       VY));                                                                      781.                                                                             endmodule // fix.sub.-- deco                                               782.                                                                             `include "defines.h" // comments                                           783.                                                                             ///////////////////////////////////////////////////////////////////        784.                                                                             // MODULE:  FXDISREG                                                       785.                                                                             // MODIFICATIONS:                                                          786.                                                                             //                                                                         787.                                                                             `define FXDISREG 1.10                                                      788.                                                                             //                                                                         789.                                                                             // DESCRIPTION: This module is just a register which resets to `h00.       790.                                                                             // Data is written to it while the WR signal is high                       791.                                                                             // NOTE: This module uses the Toshiba structural element LD3               792.                                                                             module fxdisreg (D.sub.-- IN, WR, RESET, D.sub.-- OUT);                    793.                                                                             input [7:0] D.sub.-- IN;                                                   794.                                                                             input   WR, RESET;                                                         795.                                                                             output [7:0] D.sub.-- OUT;                                                 796.                                                                             wire [7:0] D.sub.-- OUT;                                                   797.                                                                             wire SET=!RESET; // since the LD3 device has a low true reset              798.                                                                             wire NWR=!WR;                                                              799.                                                                             // latch connection allows an asynchronous reset to ALL ZEROS              800.                                                                             // changed to positive edge D to fix unknowns on PROG and TAP              801.                                                                             FD2 B7 (D.sub.-- OUT[7],,D.sub.-- IN[7],NWR,SET); // edge device           802.                                                                             FD2 B6 (D.sub.-- OUT[6],,D.sub.-- IN[6],NWR,SET); // edge device           803.                                                                             LD3 B5 (D.sub.-- OUT[5],,D.sub.-- IN[5],WR,SET);                           804.                                                                             LD3 B4 (D.sub.-- OUT[4],,D.sub.-- IN[4],WR,SET);                           805.                                                                             LD3 B3 (D.sub.-- OUT[3],,D.sub.-- IN[3],WR,SET);                           806.                                                                             LD3 B2 (D.sub.-- OUT[2],,D.sub.-- IN[2],WR,SET);                           807.                                                                             LD3 B1 (D.sub.-- OUT[1],,D.sub.-- IN[1],WR,SET);                           808.                                                                             LD3 B0 (D.sub.-- OUT[0],,D.sub.-- IN[0],WR,SET);                           809.                                                                             endmodule                                                                  810.                                                                             `include "defines.h" // comment                                            812.                                                                             // MODULE:  IOSEL                                                          813.                                                                             // MODIFICATIONS:                                                          814.                                                                             //  improve operation                                                      815.                                                                             //                                                                         816.                                                                             `define IOSEL.sub.-- REV 1.10                                              817.                                                                             //                                                                         818.                                                                             // DESCRIPTION:                                                            819.                                                                             // This module is a programmable IO select. It receives the contents       820.                                                                             // of a LADD REG (lower address), UADD.sub.-- REG (upper address), and        the                                                                        821.                                                                             // MASK.sub.-- REG to determine a match against the contents of            822.                                                                             // the address bus. Further selection qualification includes matchcs          of                                                                         823.                                                                             // the contents of a CMD.sub.-- REG against command conditions for the        access.                                                                    824.                                                                             module iosel(ADDRESS, AEN, CMD.sub.-- REG, DATA.sub.-- DEC, IOR, IOW,         I.sub.-- MTCH, LADD.sub.-- REG                                             825.                                                                             , MASK.sub.-- REG, PRIVY, PROG, SECURE, UADD.sub.-- REG, IGNORE.sub.--        RD, IO16, IO.sub.-- SEL, XA.sub.-- SEL                                     826.                                                                             , XB.sub.-- SEL);                                                          827.                                                                             input AEN, DATA.sub.-- DEC, IOR, IOW, I.sub.-- MTCH, PRIVY, PROG,             SECURE;                                                                    828.                                                                             output IGNORE.sub.-- RD, IO16, IO.sub.-- SEL, XA.sub.-- SEL, XB.sub.--        SEL;                                                                       829.                                                                             input [7:0] UADD.sub.-- REG;                                               530.                                                                             input [7:0] MASK.sub.-- REG;                                               831.                                                                             input [7:0] LADD.sub.-- REG;                                               832.                                                                             input [7:0] CMD.sub.-- REG;                                                833.                                                                             input [15:0] ADDRESS;                                                      834.                                                                             wire STICKY; // This bit is used during index decode mode. The sticky         bit is set and turns                                                       835.                                                                                // on the IOSEL if the write to the indexed LADD.sub.-- REG has            bit[0] is a 1.                                                             836.                                                                                // If bit[0] is not a 1, STICKY is cleared                              837.                                                                             //  7 6 5 4 3 2 1 0                                                        838.                                                                             // REGISTER ASSUMPTION INDEXED XA.sub.-- USE XB.sub.-- USE IOW.sub.--         OK IOR.sub.-- OK SECURE PRIVY IO16                                         839.                                                                             wire ADD.sub.-- MTCH = {UADD.sub.-- REG,LADD.sub.-- REG} = = {ADDRESS[1       5:8],(˜(MASK.sub.-- REG) & ADDRESS[7:0])};                           840.                                                                             wire IDX.sub.-- MTCH = I.sub.-- MTCH && DATA.sub.-- DEC;                   841.                                                                             wire SEL.sub.-- MTCH = ((ADD.sub.-- MTCH && !CMD.sub.-- REG[7])               ∥ (IDX.sub.-- MTCH && CMD.sub.-- REG[7])) &&                      842.                                                                                ((CMD.sub.-- REG[2] && !SECURE) ∥ !CMD.sub.-- REG[2]) &&       843.                                                                                ((CMD.sub.-- REG[1] && PRIVY) ∥ !CMD.sub.-- REG[1]) &&         844.                                                                                `AEN && !PROG;                                                          845.                                                                             wire CMD.sub.-- MTCH = CMD.sub.-- REG[4:3]==2`b00 ∥ CMD.sub.--        REG[3] && IOR ∥ CMD.sub.-- REG[4] && IOW;                        846.                                                                             wire IO.sub.-- SEL = (SEL.sub.-- MTCH && CMD.sub.-- MTCH) ∥          !PROG && CMD.sub.-- REG[7] && STICKY;                                      847.                                                                             // enable the appropriate BUS; note: illegal combination of CMD.sub.--        REG[6:5] = 11 disables all BUSes                                           848.                                                                             wire XA.sub.-- SEL = CMD.sub.-- REG[6:5]==2`b01 && SEL.sub.-- MTCH;        849.                                                                             wire XB.sub.-- SEL = CMD.sub.-- REG[6:5]==2`b10 && SEL.sub.-- MTCH;        850.                                                                             wire SEL = XA.sub.-- SEL ∥ XB.sub.-- SEL;                         851.                                                                             wire IGNORE.sub.-- RD = SEL && (CMD.sub.-- REG[4:3]==2`b10); // fix of        a bug: this signal should only                                             852.                                                                                         // be asserted if this sel is intended to                      853.                                                                                         // be write only, not address decode                           854.                                                                             YFD1 U2 (.D(MASK.sub.-- REG[0]),.CP(!IOW),.Q(STICKY));                     855.                                                                             wire IO16 = SEL.sub.-- MTCH && CMD.sub.-- RED[0];                          856.                                                                             endmodule // iosel                                                         857.                                                                             ///////////////////////////////////////////////////////////////////        858.                                                                             // MODULE:  IRQ.sub.-- DEC                                                 859.                                                                             // MODIFICATIONS:                                                          860.                                                                             //                                                                         861.                                                                             `define IRQ.sub.-- DEC.sub.-- REV 1.00                                     862.                                                                             //                                                                         863.                                                                             // DESCRIPTION:                                                            864.                                                                             // This block is the core element in the IRQ.sub.-- SW block that             maps                                                                       865.                                                                             // the given input to one of the outputs based on selects and              866.                                                                             // proper enables                                                          867.                                                                             ///////////////////////////////////////////////////////////////////        868.                                                                             module irq.sub.-- dec (REQ.sub.-- IN SEL, DIS, PROG, REQ.sub.-- OUT);      869.                                                                             input REQ.sub.-- IN, DIS, PROG:                                            870.                                                                             input [2:0] SEL;                                                           871.                                                                             output [5:0] REQ.sub.-- OUT;                                               872.                                                                             wire [5:0] REQ.sub.-- OUT={6{(!PROG && !DIS && REQ.sub.-- IN)}} & (        873.                                                                               {SEL==3`b101,SEL==3`b100,SEL==3`b011,SEL==3`b010,SEL==3`b001,SEL==3`b       000});                                                                     874.                                                                             endmodule // irq.sub.-- dec                                                875.                                                                             ///////////////////////////////////////////////////////////////////        876.                                                                             // MODULE:  IRQ.sub.-- SWITCH                                              877.                                                                             // MODIFICATIONS:                                                          878.                                                                             //     (revamped to be decodes instead of muxes)                           879.                                                                             //                                                                         880.                                                                             `define IRQSWCH.sub.-- REV 1.00                                            881.                                                                             //                                                                         882.                                                                             // DESCRIPTION:                                                            883.                                                                             // This block switches 6 device-side IRQs                                  884.                                                                             // to 8 system side IRQs. Note that multiple IRQ ins can share an          885.                                                                             // IRQ out.                                                                886.                                                                             ///////////////////////////////////////////////////////////////////        887.                                                                             module irqswch( DIS0, DIS1, DIS2, DIS3, D1S4, DIS5, PROG, REQ.sub.--          IN, SEC0, SEC1                                                             888.                                                                             , SEC2, SEC3, SEC4, SEC5, SEL0, SEL1, SEL2, SEL3, SEL4, SEL5,                 REQ.sub.-- OUT, SECURE                                                     889.                                                                             );                                                                         890.                                                                             input DIS0, DIS1, D1S2, DIS3, D1S4, DIS5, PROG, SEC0, SEC1, SEC2,             SEC3                                                                       891.                                                                             , SEC4, SEC5, SECURE;                                                      892.                                                                             input [2:0] SEL5;                                                          893.                                                                             input [2:0] SEL4;                                                          894.                                                                             input [2:0] SEL3;                                                          895.                                                                             input [2:0] SEL2;                                                          896.                                                                             input [2:0] SEL1;                                                          897.                                                                             input [2:0] SEL0;                                                          895.                                                                             input [5:0] REQ.sub.-- IN;                                                 899.                                                                             output [5:0] REQ.sub.-- OUT;                                               900.                                                                             wire [5:0] req0, req1, req2, req3, req4, req5;                             901.                                                                             wire [5:0] REQ.sub.-- OUT = req5 | req4 | req3              | req2 | req1 | req0;                           902.                                                                             // disable should be asserted if secure is on and the sec feature is          on.                                                                        903.                                                                             irq.sub.-- dec S0req (REQ.sub.-- IN[0], SEL0, ((SEC0 && SECURE)               ∥ DIS0), PROG, req0);                                             904.                                                                             irq.sub.-- dec S1req (REQ.sub.-- IN[1], SEL1, ((SEC1 && SECURE)               ∥ DIS1), PROG, req1);                                             905.                                                                             irq.sub.-- dec S2req (REQ.sub.-- IN[2], SEL2, ((SEC2 && SECURE)               ∥ DIS2), PROG, req2);                                             906.                                                                             irq.sub.-- dec S3req (REQ.sub.-- IN[3], SEL3, ((SEC3 && SECURE)               ∥ DIS3), PROG, req3);                                             907.                                                                             irq.sub.-- dec S4req (REQ.sub.-- IN[4], SEL4, ((SEC4 && SECURE)               ∥ DIS4), PROG, req4);                                             908.                                                                             irq.sub.-- dec S5req (REQ.sub.-- IN[5], SEL5, ((SEC5 && SECURE)               ∥ DIS5), PROG, req5);                                             909.                                                                             endmodule // irqswch                                                       910.                                                                             `include "defines.h" // comments                                           911.                                                                             ///////////////////////////////////////////////////////////////////        912.                                                                             // MODULE: IX.sub.-- DECO                                                  913.                                                                             //                                                                         914.                                                                             // MODIFICATIONS:                                                          915.                                                                             //    support the CLIO.sub.-- INHIBIT bit in index[7]                      916.                                                                             //                                                                         917.                                                                             `define IX.sub.-- DECO.sub.-- REV 1.00                                     918.                                                                             //                                                                         919.                                                                             // Description: This block asserts the Index decode lines                  920.                                                                             // when the index contains the value of the corresponding                  921.                                                                             // register. (SELXLADDs)                                                   922.                                                                             module ix.sub.-- deco( INDEX, IX.sub.-- DECODE);                           923.                                                                             input [6:0] INDEX;                                                         924.                                                                             output [15:0] IX.sub.-- DECODE;                                            925.                                                                             reg [15:0] IX.sub.-- DECODE;                                               926.                                                                             always @(INDEX) begin                                                      927.                                                                               case ({1`b0, INDEX }) // mask off index bit 7                            928.                                                                                       // which determines wether CLIO returns data                     929.                                                                                       // on reads or the index.sub.-- decoded device does              930.                                                                               `SEL0LADD: IX.sub.-- DECODE=16`b0000000000000001;                        931.                                                                               `SEL1LADD: IX.sub.-- DECODE=16`b0000000000000010;                        932.                                                                               `SEL2LADD: IX.sub.-- DECODE=16`b0000000000000100;                        933.                                                                               `SEL3LADD: IX.sub.-- DECODE=16`b0000000000001000;                        934.                                                                               `SEL4LADD: IX.sub.-- DECODE=16`b0000000000010000;                        935.                                                                               `SEL5LADD: IX.sub.-- DECODE=16`b0000000000100000;                        936.                                                                               `SEL6LADD: IX.sub.-- DECODE=16`b0000000001000000;                        937.                                                                               `SEL7LADD: IX.sub.-- DECODE=16`b0000000010000000;                        938.                                                                               `SEL8LADD: IX.sub.-- DECODE=16`b0000000100000000;                        939.                                                                               `SEL9LADD: IX.sub.-- DECODE=16`b0000001000000000;                        940.                                                                               `SEL10LADD: IX.sub.-- DECODE=16`b0000010000000000;                       941.                                                                               `SEL11LADD: IX.sub.-- DECODE=16`b0000100000000000;                       942.                                                                               `SEL12LADD: IX.sub.-- DECODE=16`b0001000000000000;                       943.                                                                               `SEL13LADD: IX.sub.-- DECODE=16`b0010000000000000;                       944.                                                                               `SEL14LADD: IX.sub.-- DECODE=16`b0100000000000000;                       945.                                                                               `SEL15LADD: IX.sub.-- DECODE=16`b1000000000000000;                       946.                                                                             default:  IX.sub.-- DECODE=16`b0000000000000000;                           947.                                                                             endcase                                                                    948.                                                                             end                                                                        949.                                                                             endmodule // ix.sub.-- deco                                                950.                                                                             ///////////////////////////////////////////////////////////////////        951.                                                                             // This module was created to force synopsys                               952.                                                                             // to utilize a specific 8 bit latch architecture.                         953.                                                                             // In this case it forces the Toshiba 4 bit latch                          954.                                                                             // library element to be used as the building block.                       955.                                                                             //                                                                         956.                                                                             //                                                                         957.                                                                             `define LTCH8.sub.-- REV 1.00                                              958.                                                                             //                                                                         959.                                                                             // DESCRIPTION: This module was created to froce Synopsys to use           960.                                                                             // then YLDI4B 4 bit latch element from the Toshiba library for            961.                                                                             // optimal size efficientcy                                                962.                                                                             module ltch8 (ind, wr, outd);                                              963.                                                                             input [7:0] ind;                                                           964.                                                                             input    wr;                                                               965.                                                                             output [7:0] outd;                                                         966.                                                                             wire [7:0] outd;                                                           967.                                                                             // instatiate Toshiba 140G library device (4 bit latch)                    968.                                                                             YLD14B U1 (outd[3],,outd[2],,outd[1],,outd[0],,ind[3],ind[2],ind[1],ind       [0],wr);                                                                   969.                                                                             YLD14B U2 (outd[7],,outd[6],,outd[5],,outd[4],,ind[7],ind[6],ind[5],ind       [4],wr);                                                                   970.                                                                             // This code is a scructural independant version of the 8 bit latch.       971.                                                                             // reg [7:0] outd:                                                         972.                                                                             // always @(wr or ind) begin                                               973.                                                                             // if (wr) outd=ind;                                                       974.                                                                             // end                                                                     975.                                                                             endmodule                                                                  976.                                                                             ///////////////////////////////////////////////////////////////////        977.                                                                             // MODULE: Prog.sub.-- DLY                                                 978.                                                                             // PURPOSE: This programmable tap delay element provides                   979.                                                                             // a means for selecting one of 4 delay taps. The default                  980.                                                                             // delay on sel=00 is typical delay of 36 ns. 48, 60, and                  981.                                                                             // 24 are also selectable. designed for use with 140G                      982.                                                                             // speed delays                                                            983.                                                                             // Note: Be sure to account for other delays in the path                   984.                                                                             // outside of this elements.                                               985.                                                                             //                                                                         986.                                                                             `define PROG.sub.-- DLY.sub.-- REV 1.00                                    987.                                                                             //                                                                         988.                                                                             // Note: This module uses Toshiba 140G specific structures                 989.                                                                             module prog.sub.-- dly (Z, A, SEL0, SEL1);                                 990.                                                                             input A, SEL0, SEL1;                                                       991                                                                              output Z;                                                                  992.                                                                             wire Z;                                                                    993.                                                                             YDLY3 U1 (.Z(TAP1), A(A)); // typ=4-12                                     994.                                                                             YDLY3 U2 (.Z(TAP2), A(TAP1)); // typ=8-24                                  995.                                                                             YDLY3 U3 (.Z(TAP3), A(TAP2)); // typ=12-36                                 996.                                                                             YDLY3 U4 (.Z(TAP4), A(TAP3)); // typ=16-48                                 997.                                                                             YDLY3 U5 (.Z(TAP5), A(TAP4)); // typ=20-60                                 998.                                                                             YDLY3 U7 (.Z(TAP6), A(TAP5)); // typ=24-72                                 999.                                                                             MUX41 U6 (.Z(Z),.D0(TAP5),.D1(TAP6),.D2(TAP4),.D3(TAP3),                   1000.                                                                              .A(SEL0),.B(SEL1));                                                      1001.                                                                            endmodule // prog.sub.-- dly                                               1002.                                                                            `include "defines.h" // comments                                           1003.                                                                            ///////////////////////////////////////////////////////////////////        1004.                                                                            // MODULE: REGCNTRL                                                        1005.                                                                            // MODIFICATION:                                                           1006.                                                                            // to 6 bits                                                               1007.                                                                            // delay                                                                   1008.                                                                            // features                                                                1009.                                                                            // so that CLIO rd data can be inhibited                                   1010.                                                                            // during index decoded IOR                                                1011.                                                                            // during writes only                                                      1012.                                                                            //  be 8`hFF                                                               1013.                                                                            //  conditions on TAP.sub.-- SEL and PROG                                  1014.                                                                            //                                                                         1015.                                                                            `define REGCNTRL.sub.-- REV 1.20                                           1016.                                                                            module regcntrl(ADDRESS, AEN, D.sub.-- IN, IOR, IOW, PRIVY, RESET,            SECURE, DATA.sub.-- DEC                                                    1017.                                                                            , DMASW10, DMASW32, DMASW54, D.sub.-- OUT, FIXDIS, INDEX, IRQSEC,             IRQSW10                                                                    1018.                                                                            , IRQSW32, IRQSW54, OUT.sub.-- EN, PROG, SEL0CMD, SEL0LADD, SEL0MASK,         SEL0UADD                                                                   1019.                                                                            , SEL10CMD, SEL10LADD, SEL10MASK, SEL10UADD, SEL11CMD, SEL11LADD,             SEL11MASK                                                                  1020.                                                                            , SEL11UADD, SEL12CMD, SEL12LADD, SEL12MASK, SEL12UADD, SEL13CMD,             SEL13LADD                                                                  1021.                                                                            , SEL13MASK, SEL13UADD, SEL14CMD, SEL14LADD, SEL14MASK, SEL14UADD,            SEL15CMD                                                                   1022.                                                                            , SEL15LADD, SEL15MASK, SEL15UADD, SEL1CMD, SEL1LADD, SEL1MASK,               SEL1UADD                                                                   1023.                                                                            , SEL2CMD, SEL2LADD, SEL2MASK, SEL2UADD, SEL3CMD, SEL3LADD, SEL3MASK,         SEL3UADD                                                                   1024.                                                                            , SEL4CMD, SEL4LADD, SEL4MASK, SEL4UADD, SEL5CMD, SEL5LADD, SEL5MASK,         SEL5UADD                                                                   1025.                                                                            , SEL6CMD, SEL6LADD, SEL6MASK, SEL6UADD, SEL7CMD, SEL7LADD, SEL7MASK,         SEL7UADD                                                                   1026.                                                                            , SEL8CMD, SEL8LADD, SEL8MASK, SEL8UADD, SEL9CMD, SEL9LADD, SEL9MASK,         SEL9UADD                                                                   1027.                                                                            , XA.sub.-- SEL);                                                          1028.                                                                            input AEN, IOR, IOW, PRIVY, RESET, SECURE;                                 1029.                                                                            output DATA.sub.-- DEC, OUT.sub.-- EN, PROG, XA.sub.-- SEL;                1030.                                                                            input [7:0] D.sub.-- IN;                                                   1031.                                                                            input [15:0] ADDRESS;                                                      1032.                                                                            output [7:0] SEL9UADD;                                                     1033.                                                                            output [7:0] SEL9MASK,                                                     1034.                                                                            output [7:0] SEL9LADD;                                                     1035.                                                                            output [7:0] SEL9CMD;                                                      1036.                                                                            output [7:0] SEL8UADD;                                                     1037.                                                                            output [7:0] SEL8MASK;                                                     1038.                                                                            output [7:0] SEL8LADD;                                                     1039.                                                                            output [7:0] SEL8CMD;                                                      1040.                                                                            output [7:0] SEL7UADD;                                                     1041.                                                                            output [7:0] SEL7MASK:                                                     1042.                                                                            output [7:0] SEL7LADD;                                                     1043.                                                                            output [7:0] SEL7CMD;                                                      1044.                                                                            output [7:0] SEL6UADD:                                                     1045.                                                                            output [7:0] SEL6MASK:                                                     1046.                                                                            output [7:0] SEL6LADD;                                                     1047.                                                                            output [7:0] SEL6CMD;                                                      1048.                                                                            output [7:0] SEL5UADD;                                                     1049.                                                                            output [7:0] SEL5MASK:                                                     1050.                                                                            output [7:0] SEL5LADD;                                                     1051.                                                                            output [7:0] SEL5CMD;                                                      1052.                                                                            output [7:0] SEL4UADD;                                                     1053.                                                                            output [7:0] SEL4MASK;                                                     1054.                                                                            output [7:0] SEL4LADD;                                                     1055.                                                                            output [7:0] SEL4CMD;                                                      1056.                                                                            output [7:0] SEL3UADD:                                                     1057.                                                                            output [7:0] SEL3MASK:                                                     1058.                                                                            output [7:0] SEL3LADD;                                                     1059.                                                                            output [7:0] SEL3CMD:                                                      1060.                                                                            output [7:0] SEL2UADD;                                                     1061.                                                                            output [7:0] SEL2MASK;                                                     1062.                                                                            output [7:0] SEL2LADD;                                                     1063.                                                                            output [7:0] SEL2CMD;                                                      1064.                                                                            output [7:0] SEL1UADD:                                                     1065.                                                                            output [7:0] SEL1MASK;                                                     1066.                                                                            output [7:0] SEL1LADD;                                                     1067.                                                                            output [7:0] SEL1CMD;                                                      1068.                                                                            output [7:0] SEL15UADD;                                                    1069.                                                                            output [7:0] SEL15MASK;                                                    1070.                                                                            output [7:0] SEL15LADD;                                                    1071.                                                                            output [7:0] SEL15CMD;                                                     1072.                                                                            output [7:0] SEL14UADD;                                                    1073.                                                                            output [7:0] SEL14MASK;                                                    1074.                                                                            output [7:0] SEL14LADD;                                                    1075.                                                                            output [7:0] SEL14CMD;                                                     1076.                                                                            output [7:0] SEL13UADD;                                                    1077.                                                                            output [7:0] SEL13MASK;                                                    1078.                                                                            output [7:0] SEL13LADD;                                                    1079.                                                                            output [7:0] SEL13CMD;                                                     1080.                                                                            output [7:0] SEL12UADD;                                                    1081.                                                                            output [7:0] SEL12MASK;                                                    1082.                                                                            output [7:0] SEL12LADD;                                                    1083.                                                                            output [7:0] SEL12CMD;                                                     1084.                                                                            output [7:0] SEL11UADD;                                                    1085.                                                                            output [7:0] SEL11MASK;                                                    1086.                                                                            output [7:0] SEL11LADD;                                                    1087.                                                                            output [7:0] SEL11CMD;                                                     1088.                                                                            output [7:0] SEL10UADD;                                                    1089.                                                                            output [7:0] SEL10MASK;                                                    1090.                                                                            output [7:0] SEL10LADD;                                                    1091.                                                                            output [7:0] SEL10CMD;                                                     1092.                                                                            output [7:0] SEL0UADD;                                                     1093.                                                                            output [7:0] SEL0MASK;                                                     1094.                                                                            output [7:0] SEL0LADD;                                                     1095.                                                                            output [7:0] SEL0CMD;                                                      1096.                                                                            output [7:0] IRQSW54;                                                      1097.                                                                            output [7:0] IRQSW32;                                                      1098.                                                                            output [7:0] IRQSW10;                                                      1099.                                                                            output [7:0] IRQSEC;                                                       1100.                                                                            output [6:0] INDEX;                                                        1101.                                                                            output [5:0] FIXDIS;                                                       1102.                                                                            output [7:0] D.sub.-- OUT;                                                 1103.                                                                            output [7:0] DMASW54;                                                      1104.                                                                            output [7:0] DMASW32;                                                      1105.                                                                            output [7:0] DMASW10;                                                      1106.                                                                            reg     OUT.sub.-- EN;                                                     1107.                                                                            wire [7:0] index;                                                          1108.                                                                            wire [6:0] INDEX = index[6:0];                                             1109.                                                                            // This INDEX latch holds the register INDEX value                         1110.                                                                            wire [7:0]  IOBASE, fxdis;                                                 1111.                                                                            wire [5:0] FIXDIS = fxdis[5:0];                                            1112.                                                                            wire [7:0] SEL0CMD                                                         1113.                                                                            , SEL1CMD                                                                  1114.                                                                            , SEL2CMD                                                                  1115.                                                                            , SEL3CMD                                                                  1116.                                                                            , SEL4CMD                                                                  1117.                                                                            , SEL5CMD                                                                  1118.                                                                            , SEL6CMD                                                                  1119.                                                                            , SEL7CMD                                                                  1120.                                                                            , SEL8CMD                                                                  1121.                                                                            , SEL9CMD                                                                  1122.                                                                            , SEL10CMD                                                                 1123.                                                                            , SEL11CMD                                                                 1124.                                                                            , SEL12CMD                                                                 1125.                                                                            , SEL13CMD                                                                 1126.                                                                            , SEL14CMD                                                                 1127.                                                                            , SEL15CMD                                                                 1128.                                                                            , SEL0LADD                                                                 1129.                                                                            , SEL1LADD                                                                 1130.                                                                            , SEL2LADD                                                                 1131.                                                                            , SEL3LADD                                                                 1132.                                                                            , SEL4LADD                                                                 1133.                                                                            , SEL5LADD                                                                 1134.                                                                            , SEL6LADD                                                                 1135.                                                                            , SEL7LADD                                                                 1136.                                                                            , SEL8LADD                                                                 1137.                                                                            , SEL9LADD                                                                 1138.                                                                            , SEL10LADD                                                                1139.                                                                            , SEL11LADD                                                                1140.                                                                            , SEL12LADD                                                                1141.                                                                            , SEL13LADD                                                                1142.                                                                            , SEL14LADD                                                                1143.                                                                            , SEL15LADD                                                                1144.                                                                            , SEL0UADD                                                                 1145.                                                                            , SEL1UADD                                                                 1146.                                                                            , SEL2UADD                                                                 1147.                                                                            , SEL3UADD                                                                 1148.                                                                            , SEL4UADD                                                                 1149.                                                                            , SEL5UADD                                                                 1150.                                                                            , SEL6UADD                                                                 1151.                                                                            , SEL7UADD                                                                 1152.                                                                            , SEL8UADD                                                                 1153.                                                                            , SEL9UADD                                                                 1154.                                                                            , SEL10UADD                                                                1155.                                                                            , SEL11UADD                                                                1156.                                                                            , SEL12UADD                                                                1157.                                                                            , SEL13UADD                                                                1158.                                                                            , SEL14UADD                                                                1159.                                                                            , SEL15UADD                                                                1160.                                                                            , SEL0MASK                                                                 1161.                                                                            , SEL1MASK                                                                 1162.                                                                            , SEL2MASK                                                                 1163.                                                                            , SEL3MASK                                                                 1164.                                                                            , SEL4MASK                                                                 1165.                                                                            , SEL5MASK                                                                 1166.                                                                            , SEL6MASK                                                                 1167.                                                                            , SEL7MASK                                                                 1168.                                                                            , SEL8MASK                                                                 1169.                                                                            , SEL9MASK                                                                 1170.                                                                            , SEL10MASK                                                                1171.                                                                            , SEL11MASK                                                                1172.                                                                            , SEL12MASK                                                                1173.                                                                            , SEL13MASK                                                                1174.                                                                            , SEL14MASK                                                                1175.                                                                            , SEL15MASK                                                                1176.                                                                            , IRQSW10                                                                  1177.                                                                            , IRQSW32                                                                  1178.                                                                            , IRQSW54                                                                  1179.                                                                            , DMASW10                                                                  1180.                                                                            , DMASW32                                                                  1181.                                                                            , DMASW54                                                                  1182.                                                                            , IRQSEC;                                                                  1183.                                                                            // This INDEX and data port are programmable based off                     1184.                                                                            // of IOBASE register                                                      1185.                                                                            wire uadd.sub.-- zero = ADDRESS[15:8]==8`h00;                              1186.                                                                            wire base.sub.-- mtch = uadd.sub.-- zero &&                                1187.                                                                               (ADDRESS[7:3]==IOBASE[7:3] && PRIVY && !AEN);                           1188.                                                                            wire INDEX.sub.-- DEC = (base.sub.-- mtch && ADDRESS[2:0]==3`b000);        1189.                                                                            wire DATA.sub.-- DEC = (base mtch && ADDRESS[2:0]==IOBASE[2:0]);           1190.                                                                            wire data.sub.-- wr = DATA.sub.-- DEC && IOW && !SECURE;                   1191.                                                                            wire index wt = INDEX.sub.-- DEC && IOW;                                   1192.                                                                            reg [7:0] data.sub.-- out;                                                 1193.                                                                            wire [7:0] D.sub.-- OUT = INDEX.sub.-- DEC ? index : data.sub.-- out;      1194.                                                                            wire D.sub.-- XA = DATA.sub.-- DEC;                                        1195.                                                                            wire I.sub.-- XA = INDEX.sub.-- DEC;                                       1196.                                                                            // inhibit turning XREAD.sub.-- on during reads of index.sub.--               decoded iosels                                                             1197.                                                                            wire XA.sub.-- SEL = (D.sub.-- XA && !index[7]) ∥ I.sub.--           XA;                                                                        1198.                                                                            wire WR.sub.-- SEL0CMD = index==`SEL0CMD && data.sub.-- wr;                1199.                                                                            wire WR.sub.-- SEL1CMD = index==`SEL1CMD && data.sub.-- wr;                1200.                                                                            wire WR.sub.-- SEL2CMD = index==`SEL2CMD && data.sub.-- wr;                1201.                                                                            wire WR.sub.-- SEL3CMD = index==`SEL3CMD && data.sub.-- wr;                1202.                                                                            wire WR.sub.-- SEL4CMD = index==`SEL4CMD && data.sub.-- wr;                1203.                                                                            wire WR.sub.-- SEL5CMD = index==`SEL5CMD && data.sub.-- wr;                1204.                                                                            wire WR.sub.-- SEL6CMD = index==`SEL6CMD && data.sub.-- wr;                1205.                                                                            wire WR.sub.-- SEL7CMD = index==`SEL7CMD && data.sub.-- wr;                1206.                                                                            wire WR.sub.-- SEL8CMD = index==`SEL8CMD && data.sub.-- wr;                1207.                                                                            wire WR.sub.-- SEL9CMD = index==`SEL9CMD && data.sub.-- wr;                1208.                                                                            wire WR.sub.-- SEL10CMD = index==`SEL10CMD && data.sub.-- wr;              1209.                                                                            wire WR.sub.-- SEL11CMD = index==`SEL11CMD && data.sub.-- wr;              1210.                                                                            wire WR.sub.-- SEL12CMD = index==`SEL12CMD && data.sub.-- wr;              1211.                                                                            wire WR.sub.-- SEL13CMD = index==`SEL13CMD && data.sub.-- wr;              1212.                                                                            wire WR.sub.-- SEL14CMD = index==`SEL14CMD && data.sub.-- wr;              1213.                                                                            wire WR.sub.-- SEL15CMD = index==`SEL15CMD && data.sub.-- wr;              1214.                                                                            wire WR.sub.-- SEL0LADD = index==`SEL0LADD && data.sub.-- wr;              1215.                                                                            wire WR.sub.-- SEL1LADD = index==`SEL1LADD && data.sub.-- wr;              1216.                                                                            wire WR.sub.-- SEL2LADD = index==`SEL2LADD && data.sub.-- wr;              1217.                                                                            wire WR.sub.-- SEL3LADD = index==`SEL3LADD && data.sub.-- wr;              1218.                                                                            wire WR.sub.-- SEL4LADD = index==`SEL4LADD && data.sub.-- wr;              1219.                                                                            wire WR.sub.-- SEL5LADD = index==`SEL5LADD && data.sub.-- wr;              1220.                                                                            wire WR.sub.-- SEL6LADD = index==`SEL6LADD && data.sub.-- wr;              1221.                                                                            wire WR.sub.-- SEL7LADD = index==`SEL7LADD && data.sub.-- wr;              1222.                                                                            wire WR.sub.-- SEL8LADD = index==`SEL8LADD && data.sub.-- wr;              1223.                                                                            wire WR.sub.-- SEL9LADD = index==`SEL9LADD && data.sub.-- wr;              1224.                                                                            wire WR.sub.-- SEL10LADD = index==`SEL10LADD && data.sub.-- wr;            1225.                                                                            wire WR.sub.-- SEL11LADD = index==`SEL11LADD && data.sub.-- wr;            1226.                                                                            wire WR.sub.-- SEL12LADD = index==`SEL12LADD && data.sub.-- wr;            1227.                                                                            wire WR.sub.-- SEL13LADD = index==`SEL13LADD && data.sub.-- wr;            1228.                                                                            wire WR.sub.-- SEL14LADD = index==`SEL14LADD && data.sub.-- wr;            1229.                                                                            wire WR.sub.-- SEL15LADD = index==`SEL15LADD && data.sub.-- wr;            1230.                                                                            wire WR.sub.-- SEL0UADD = index==`SEL0UADD && data.sub.-- wr;              1231.                                                                            wire WR.sub.-- SEL1UADD = index==`SEL1UADD && data.sub.-- wr;              1232.                                                                            wire WR.sub.-- SEL2UADD = index==`SEL2UADD && data.sub.-- wr;              1233.                                                                            wire WR.sub.-- SEL3UADD = index==`SEL3UADD && data.sub.-- wr;              1234.                                                                            wire WR.sub.-- SEL4UADD = index==`SEL4UADD && data.sub.-- wr;              1235.                                                                            wire WR.sub.-- SEL5UADD = index==`SEL5UADD && data.sub.-- wr;              1236.                                                                            wire WR.sub.-- SEL6UADD = index==`SEL6UADD && data.sub.-- wr;              1237.                                                                            wire WR.sub.-- SEL7UADD = index==`SEL7UADD && data.sub.-- wr;              1238.                                                                            wire WR.sub.-- SEL8UADD = index==`SEL8UADD && data.sub.-- wr;              1239.                                                                            wire WR.sub.-- SEL9UADD = index==`SEL9UADD && data.sub.-- wr;              1240.                                                                            wire WR.sub.-- SEL10UADD = index==`SEL10UADD && data.sub.-- wr;            1241.                                                                            wire WR.sub.-- SEL11UADD = index==`SEL11UADD && data.sub.-- wr;            1242.                                                                            wire WR.sub.-- SEL12UADD = index==`SEL12UADD && data.sub.-- wr;            1243.                                                                            wire WR.sub.-- SEL13UADD = index==`SEL13UADD && data.sub.-- wr;            1244.                                                                            wire WR.sub.-- SEL14UADD = index==`SEL14UADD && data.sub.-- wr;            1245.                                                                            wire WR.sub.-- SEL15UADD = index==`SEL15UADD && data.sub.-- wr;            1246.                                                                            wire WR.sub.-- SEL0MASK = index==`SEL0MASK && data.sub.-- wr;              1247.                                                                            wire WR.sub.-- SEL1MASK = index==`SEL1MASK && data.sub.-- wr;              1248.                                                                            wire WR.sub.-- SEL2MASK = index==`SEL2MASK && data.sub.-- wr;              1249.                                                                            wire WR.sub.-- SEL3MASK = index==`SEL3MASK && data.sub.-- wr;              1250.                                                                            wire WR.sub.-- SEL4MASK = index==`SEL4MASK && data.sub.-- wr;              1251.                                                                            wire WR.sub.-- SEL5MASK = index==`SEL5MASK && data.sub.-- wr;              1252.                                                                            wire WR.sub.-- SEL6MASK = index==`SEL6MASK && data.sub.-- wr;              1253.                                                                            wire WR.sub.-- SEL7MASK = index==`SEL7MASK && data.sub.-- wr;              1254.                                                                            wire WR.sub.-- SEL8MASK = index==`SEL8MASK && data.sub.-- wr;              1255.                                                                            wire WR.sub.-- SEL9MASK = index==`SEL9MASK && data.sub.-- wr;              1256.                                                                            wire WR.sub.-- SEL10MASK = index==`SEL10MASK && data.sub.-- wr;            1257.                                                                            wire WR.sub.-- SEL11MASK = index==`SEL11MASK && data.sub.-- wr;            1258.                                                                            wire WR.sub.-- SEL12MASK = index==`SEL12MASK && data.sub.-- wr;            1259.                                                                            wire WR.sub.-- SEL13MASK = index==`SEL13MASK && data.sub.-- wr;            1260.                                                                            wire WR.sub.-- SEL14MASK = index==`SEL14MASK && data.sub.-- wr;            1261.                                                                            wire WR.sub.-- SEL15MASK = index==`SEL15MASK && data.sub.-- wr;            1262.                                                                            wire WR.sub.-- IOBASE =index==`IOBASE && data.sub.-- wr;                   1263.                                                                            wire WR.sub.-- FlXDIS =index==`FIXDIS && data.sub.-- wr;                   1264.                                                                            wire WR.sub.-- IRQSW10 =index==`IRQSW10 && data.sub.-- wr;                 1265.                                                                            wire WR.sub.-- IRQSW32 =index==`IRQSW32 && data.sub.-- wr;                 1266.                                                                            wire WR.sub.-- IRQSW54 =index==`IRQSW54 && data.sub.-- wr;                 1267.                                                                            wire WR.sub.-- IRQSEC =index==`IRQSEC && data.sub.-- wr;                   1268.                                                                            wire WR.sub.-- DMASW10 =index==`DMASW10 && data.sub.-- wr;                 1269.                                                                            wire WR.sub.-- DMASW32 =index==`DMASW32 && data.sub.-- wr;                 1270.                                                                            wire WR.sub.-- DMASW54 =index==`DMASW54 && data.sub.-- wr;                 1271.                                                                            ltch8 R1                                                                             (D.sub.-- IN, WR.sub.-- SEL0CMD, SEL0CMD);                          1272.                                                                            ltch8 R2                                                                             (D.sub.-- IN, WR.sub.-- SEL1CMD, SEL1CMD);                          1273.                                                                            ltch8 R3                                                                             (D.sub.-- IN, WR.sub.-- SEL2CMD, SEL2CMD);                          1274.                                                                            ltch8 R4                                                                             (D.sub.-- IN, WR.sub.-- SEL3CMD, SEL3CMD);                          1275.                                                                            ltch8 R5                                                                             (D.sub.-- IN, WR.sub.-- SEL4CMD, SEL4CMD);                          1276.                                                                            ltch8 R6                                                                             (D.sub.-- IN, WR.sub.-- SEL5CMD, SEL5CMD);                          1277.                                                                            ltch8 R7                                                                             (D.sub.-- IN, WR.sub.-- SEL6CMD, SEL6CMD);                          1278.                                                                            ltch8 R8                                                                             (D.sub.-- IN, WR.sub.-- SEL7CMD, SEL7CMD);                          1279.                                                                            ltch8 R9                                                                             (D.sub.-- IN, WR.sub.-- SEL8CMD, SEL8CMD);                          1280.                                                                            ltch8 R10                                                                            (D.sub.-- IN, WR.sub.-- SEL9CMD, SEL9CMD);                          1281.                                                                            ltch8 R11                                                                            (D.sub.-- IN, WR.sub.-- SEL10CMD, SEL10CMD);                        1282.                                                                            ltch8 R12                                                                            (D.sub.-- IN, WR.sub.-- SEL11CMD, SEL11CMD);                        1283.                                                                            ltch8 R13                                                                            (D.sub.-- IN, WR.sub.-- SEL12CMD, SEL12CMD);                        1284.                                                                            ltch8 R14                                                                            (D.sub.-- IN, WR.sub.-- SEL13CMD, SEL13CMD);                        1285.                                                                            ltch8 R15                                                                            (D.sub.-- IN, WR.sub.-- SEL14CMD, SEL14CMD);                        1286.                                                                            ltch8 R16                                                                            (D.sub.-- IN, WR.sub.-- SEL15CMD, SEL15CMD);                        1287.                                                                            ltch8 R17                                                                            (D.sub.-- IN, WR.sub.-- SEL0LADD, SEL0LADD);                        1288.                                                                            ltch8 R18                                                                            (D.sub.-- IN, WR.sub.-- SEL1LADD, SEL1LADD);                        1289.                                                                            ltch8 R19                                                                            (D.sub.-- IN, WR.sub.-- SEL2LADD, SEL2LADD);                        1290.                                                                            ltch8 R20                                                                            (D.sub.-- IN, WR.sub.-- SEL3LADD, SEL3LADD);                        1291.                                                                            ltch8 R21                                                                            (D.sub.-- IN, WR.sub.-- SEL4LADD, SEL4LADD);                        1292.                                                                            ltch8 R22                                                                            (D.sub.-- IN, WR.sub.-- SEL5LADD, SEL5LADD);                        1293.                                                                            ltch8 R23                                                                            (D.sub.-- IN, WR.sub.-- SEL6LADD, SEL6LADD);                        1294.                                                                            ltch8 R24                                                                            (D.sub.-- IN, WR.sub.-- SEL7LADD, SEL7LADD);                        1295.                                                                            ltch8 R25                                                                            (D.sub.-- IN, WR.sub.-- SEL8LADD, SEL8LADD);                        1296.                                                                            ltch8 R26                                                                            (D.sub.-- IN, WR.sub.-- SEL9LADD, SEL9LADD);                        1297.                                                                            ltch8 R27                                                                            (D.sub.-- IN, WR.sub.-- SEL10LADD, SEL10LADD);                      1298.                                                                            ltch8 R28                                                                            (D.sub.-- IN, WR.sub.-- SEL11LADD, SEL11LADD);                      1299.                                                                            ltch8 R29                                                                            (D.sub.-- IN, WR.sub.-- SEL12LADD, SEL12LADD);                      1300.                                                                            ltch8 R30                                                                            (D.sub.-- IN, WR.sub.-- SEL13LADD, SEL13LADD);                      1301.                                                                            ltch8 R31                                                                            (D.sub.-- IN, WR.sub.-- SEL14LADD, SEL14LADD);                      1302.                                                                            ltch8 R32                                                                            (D.sub.-- IN, WR.sub.-- SEL15LADD, SEL15LADD);                      1303.                                                                            ltch8 R33                                                                            (D.sub.-- IN, WR.sub.-- SEL0UADD, SEL0UADD);                        1304.                                                                            ltch8 R34                                                                            (D.sub.-- IN, WR.sub.-- SEL1UADD, SEL1UADD);                        1305.                                                                            ltch8 R35                                                                            (D.sub.-- IN, WR.sub.-- SEL2UADD, SEL2UADD);                        1306.                                                                            ltch8 R36                                                                            (D.sub.-- IN, WR.sub.-- SEL3UADD, SEL3UADD);                        1307.                                                                            ltch8 R37                                                                            (D.sub.-- IN, WR.sub.-- SEL4UADD, SEL4UADD);                        1308.                                                                            ltch8 R38                                                                            (D.sub.-- IN, WR.sub.-- SEL5UADD, SEL5UADD);                        1309.                                                                            ltch8 R39                                                                            (D.sub.-- IN, WR.sub.-- SEL6UADD, SEL6UADD);                        1310.                                                                            ltch8 R40                                                                            (D.sub.-- IN, WR.sub.-- SEL7UADD, SEL7UADD);                        1311.                                                                            ltch8 R41                                                                            (D.sub.-- IN, WR.sub.-- SEL8UADD, SEL8UADD);                        1312.                                                                            ltch8 R42                                                                            (D.sub.-- IN, WR.sub.-- SEL9UADD, SEL9UADD);                        1313.                                                                            ltch8 R43                                                                            (D.sub.-- IN, WR.sub.-- SEL10UADD, SEL10UADD);                      1314.                                                                            ltch8 R44                                                                            (D.sub.-- IN, WR.sub.-- SEL11UADD, SEL11UADD);                      1315.                                                                            ltch8 R45                                                                            (D.sub.-- IN, WR.sub.-- SEL12UADD, SEL12UADD);                      1316.                                                                            ltch8 R46                                                                            (D.sub.-- IN, WR.sub.-- SEL13UADD, SEL13UADD);                      1317.                                                                            ltch8 R47                                                                            (D.sub.-- IN, WR.sub.-- SEL14UADD, SEL14UADD);                      1318.                                                                            ltch8 R48                                                                            (D.sub.-- IN, WR.sub.-- SEL15UADD, SEL15UADD);                      1319.                                                                            ltch8 R49                                                                            (D.sub.-- IN, WR.sub.-- SEL0MASK, SEL0MASK);                        1320.                                                                            ltch8 R50                                                                            (D.sub.-- IN, WR.sub.-- SEL1MASK, SEL1MASK);                        1321.                                                                            ltch8 R51                                                                            (D.sub.-- IN, WR.sub.-- SEL2MASK, SEL2MASK);                        1322.                                                                            ltch8 R52                                                                            (D.sub.-- IN, WR.sub.-- SEL3MASK, SEL3MASK);                        1323.                                                                            ltch8 R53                                                                            (D.sub.-- IN, WR.sub.-- SEL4MASK, SEL4MASK);                        1324.                                                                            ltch8 R54                                                                            (D.sub.-- IN, WR.sub.-- SEL5MASK, SEL5MASK);                        1325.                                                                            ltch8 R55                                                                            (D.sub.-- IN, WR.sub.-- SEL6MASK, SEL6MASK);                        1326.                                                                            ltch8 R56                                                                            (D.sub.-- IN, WR.sub.-- SEL7MASK, SEL7MASK);                        1327.                                                                            ltch8 R57                                                                            (D.sub.-- IN, WR.sub.-- SEL8MASK, SEL8MASK);                        1328.                                                                            ltch8 R58                                                                            (D.sub.-- IN, WR.sub.-- SEL9MASK, SEL9MASK);                        1329.                                                                            ltch8 R59                                                                            (D.sub.-- IN, WR.sub.-- SEL10MASK, SEL10MASK);                      1330.                                                                            ltch8 R60                                                                            (D.sub.-- IN, WR.sub.-- SEL11MASK, SEL11MASK);                      1331.                                                                            ltch8 R61                                                                            (D.sub.-- IN, WR.sub.-- SEL12MASK, SEL12MASK);                      1332.                                                                            ltch8 R62                                                                            (D.sub.-- IN, WR.sub.-- SEL13MASK, SEL13MASK);                      1333.                                                                            ltch8 R63                                                                            (D.sub.-- IN, WR.sub.-- SEL14MASK, SEL14MASK);                      1334.                                                                            ltch8 R64                                                                            (D.sub.-- IN, WR.sub.-- SEL15MASK, SEL15MASK);                      1335.                                                                            ltch8 R67                                                                            (D.sub.-- IN, WR.sub.-- IRQSW10, IRQSW10);                          1336.                                                                            ltch8 R72                                                                            (D.sub.-- IN, WR.sub.-- IRQSW32, IRQSW32);                          1337.                                                                            ltch8 R73                                                                            (D.sub.-- IN, WR.sub.-- IRQSW54, IRQSW54);                          1338.                                                                            ltch8 R69                                                                            (D.sub.-- IN, WR.sub.-- DMASW10, DMASW10);                          1339.                                                                            ltch8 R70                                                                            (D.sub.-- IN, WR.sub.-- DMASW32, DMASW32);                          1340.                                                                            ltch8 R71                                                                            (D.sub.-- IN, WR.sub.-- DMASW54, DMASW54);                          1341.                                                                            ltch8 R80                                                                            (D.sub.-- IN, index.sub.-- wr, index);                              1342.                                                                            // loads on trailing edge of write strobe                                  1343.                                                                            basereg R65                                                                          (D.sub.-- IN, WR.sub.-- IOBASE, RESET, IOBASE);                     1344.                                                                            // loads on trailing edge of write strobe                                  1345.                                                                            fxdisreg R66                                                                         (D.sub.-- IN, WR.sub.-- FIXDIS, RESET, fxdis);                      1346.                                                                            // loads on trailing edge of write strobe                                  1347.                                                                            fxdisreg R616                                                                        (D.sub.-- IN, WR.sub.-- IRQSEC, RESET, IRQSEC);                     1348.                                                                            always @(index or data.sub.-- wr or D.sub.-- IN)                           1349.                                                                             case (index)                                                              1350.                                                                             `SEL0CMD:                                                                             data.sub.-- out=SEL0CMD;                                          1351.                                                                             `SEL1CMD:                                                                             data.sub.-- out=SEL1CMD;                                          1352.                                                                             `SEL2CMD:                                                                             data.sub.-- out=SEL2CMD;                                          1353.                                                                             `SEL3CMD:                                                                             data.sub.-- out=SEL3CMD;                                          1354.                                                                             `SEL4CMD:                                                                             data.sub.-- out=SEL4CMD;                                          1355.                                                                             `SEL5CMD:                                                                             data.sub.-- out=SEL5CMD;                                          1356.                                                                             `SEL6CMD:                                                                             data.sub.-- out=SEL6CMD;                                          1357.                                                                             `SEL7CMD:                                                                             data.sub.-- out=SEL7CMD;                                          1358.                                                                             `SEL8CMD:                                                                             data.sub.-- out=SEL8CMD;                                          1359.                                                                             `SEL9CMD:                                                                             data.sub.-- out=SEL9CMD;                                          1360.                                                                             `SEL10CMD:                                                                            data.sub.-- out=SEL10CMD;                                         1361.                                                                             `SEL11CMD:                                                                            data.sub.-- out=SEL11CMD;                                         1362.                                                                             `SEL12CMD:                                                                            data.sub.-- out=SEL12CMD;                                         1363.                                                                             `SEL13CMD:                                                                            data.sub.-- out=SEL13CMD;                                         1364.                                                                             `SEL14CMD:                                                                            data.sub.-- out=SEL14CMD;                                         1365.                                                                             `SEL15CMD:                                                                            data.sub.-- out=SEL15CMD;                                         1366.                                                                             `SEL0LADD:                                                                            data.sub.-- out=SEL0LADD;                                         1367.                                                                             `SEL1LADD:                                                                            data.sub.-- out=SEL1LADD;                                         1368.                                                                             `SEL2LADD:                                                                            data.sub.-- out=SEL2LADD;                                         1369.                                                                             `SEL3LADD:                                                                            data.sub.-- out=SEL3LADD;                                         1370.                                                                             `SEL4LADD:                                                                            data.sub.-- out=SEL4LADD;                                         1371.                                                                             `SEL5LADD:                                                                            data.sub.-- out=SEL5LADD;                                         1372.                                                                             `SEL6LADD:                                                                            data.sub.-- out=SEL6LADD;                                         1373.                                                                             `SEL7LADD:                                                                            data.sub.-- out=SEL7LADD;                                         1374.                                                                             `SEL8LADD:                                                                            data.sub.-- out=SEL8LADD;                                         1375.                                                                             `SEL9LADD:                                                                            data.sub.-- out=SEL9LADD;                                         1376.                                                                             `SEL10LADD:                                                                           data.sub.-- out=SEL10LADD;                                        1377.                                                                             `SEL11LADD:                                                                           data.sub.-- out=SEL11LADD;                                        1378.                                                                             `SEL12LADD:                                                                           data.sub.-- out=SEL12LADD;                                        1379.                                                                             `SEL13LADD:                                                                           data.sub.-- out=SEL13LADD;                                        1380.                                                                             `SEL14LADD:                                                                           data.sub.-- out=SEL14LADD;                                        1381.                                                                             `SEL15LADD:                                                                           data.sub.-- out=SEL15LADD;                                        1382.                                                                             `SEL0UADD:                                                                            data.sub.-- out=SEL0UADD;                                         1383.                                                                             `SEL1UADD:                                                                            data.sub.-- out=SEL1UADD;                                         1384.                                                                             `SEL2UADD:                                                                            data.sub.-- out=SEL2UADD;                                         1385.                                                                             `SEL3UADD:                                                                            data.sub.-- out=SEL3UADD;                                         1386.                                                                             `SEL4UADD:                                                                            data.sub.-- out=SEL4UADD;                                         1387.                                                                             `SEL5UADD:                                                                            data.sub.-- out=SEL5UADD;                                         1388.                                                                             `SEL6UADD:                                                                            data.sub.-- out=SEL6UADD;                                         1389.                                                                             `SEL7UADD:                                                                            data.sub.-- out=SEL7UADD;                                         1390.                                                                             `SEL8UADD:                                                                            data.sub.-- out=SEL8UADD;                                         1391.                                                                             `SEL9UADD:                                                                            data.sub.-- out=SEL9UADD;                                         1392.                                                                             `SEL10UADD:                                                                           data.sub.-- out=SEL10UADD;                                        1393.                                                                             `SEL11UADD:                                                                           data.sub.-- out=SEL11UADD;                                        1394.                                                                             `SEL12UADD:                                                                           data.sub.-- out=SEL12UADD;                                        1395.                                                                             `SEL13UADD:                                                                           data.sub.-- out=SEL13UADD;                                        1396.                                                                             `SEL14UADD:                                                                           data.sub.-- out=SEL14UADD;                                        1397.                                                                             `SEL15UADD:                                                                           data.sub.-- out=SEL15UADD;                                        1398.                                                                             `SEL0MASK:                                                                            data.sub.-- out=SEL0MASK;                                         1399.                                                                             `SEL1MASK:                                                                            data.sub.-- out=SEL1MASK;                                         1400.                                                                             `SEL2MASK:                                                                            data.sub.-- out=SEL2MASK;                                         1401.                                                                             `SEL3MASK:                                                                            data.sub.-- out=SEL3MASK;                                         1402.                                                                             `SEL4MASK:                                                                            data.sub.-- out=SEL4MASK;                                         1403.                                                                             `SEL5MASK:                                                                            data.sub.-- out=SEL5MASK;                                         14&4.                                                                             `SEL6MASK:                                                                            data.sub.-- out=SEL6MASK;                                         1405.                                                                             `SEL7MASK:                                                                            data.sub.-- out=SEL7MASK;                                         1406.                                                                             `SEL8MASK:                                                                            data.sub.-- out=SEL8MASK;                                         1407.                                                                             `SEL9MASK:                                                                            data.sub.-- out=SEL9MASK;                                         1408.                                                                             `SEL10MASK:                                                                           data.sub.-- out=SEL10MASK;                                        1409.                                                                             `SEL11MASK:                                                                           data.sub.-- out=SEL11MASK;                                        1410.                                                                             `SEL12MASK:                                                                           data.sub.-- out=SEL12MASK;                                        1411.                                                                             `SEL13MASK:                                                                           data.sub.-- out=SEL13MASK;                                        1412.                                                                             `SEL14MASK:                                                                           data.sub.-- out=SEL14MASK;                                        1413.                                                                             `SEL15MASK:                                                                           data.sub.-- out=SEL15MASK;                                        1414.                                                                             `IOBASE:                                                                              data.sub.-- out=IOBASE;                                           1415.                                                                             `FIXDIS:                                                                              data.sub.-- out=fxdis;                                            1416.                                                                             `IRQSW10:                                                                             data.sub.-- out=IRQSW10;                                          1417.                                                                             `IRQSW32:                                                                             data.sub.-- out=IRQSW32;                                          1428.                                                                             `IRQSW54:                                                                             data.sub.-- out=IRQSW54;                                          1419.                                                                             `IRQSEC:                                                                              data.sub.-- out=IRQSEC;                                           1420.                                                                             `DMASW10:                                                                             data.sub.-- out=DMASW10;                                          1421.                                                                             `DMASW32:                                                                             data.sub.-- out=DMASW32;                                          1422.                                                                             `DMASW54:                                                                             data.sub.-- out=DMASW54;                                          1423.                                                                             // return FF if unknown index                                             1424.                                                                             default: data.sub.-- out=8`hFF;                                           1425.                                                                             endcase                                                                   1426.                                                                            // assign the value of the INDEX based on reset conditions or the data        value                                                                      1427.                                                                            always @(RESET or IOR) begin                                               1428.                                                                              if (RESET) OUT.sub.-- EN=0;                                              1429.                                                                              // enable the output register fort reads                                 1430.                                                                              else if (IOR && ((DATA.sub.-- DEC && !index[7]) ∥ INDEX.sub.       -- DEC)) OUT.sub.-- EN =1;                                                 1431.                                                                                // if index[7] is a 1, inhibit DATA enabled from CLIO                  1432.                                                                                // this is for index decoded iosel reads of D.sub.-- PORT              1433.                                                                              else OUT.sub.-- EN=0;                                                    1434.                                                                              end                                                                      1435.                                                                            // finally, the PROG signal is derived out of FIXDIS register              1436.                                                                            // only when it is not changing. (It will always be known since it is         now                                                                        1437.                                                                            // an edge triggered storage elemtent)                                     1438.                                                                            wire PROG=!fxdis[7];                                                       1439.                                                                            endmodule // regcntrl                                                      1440.                                                                            `include "defines.h" // comments                                           1441.                                                                            ///////////////////////////////////////////////////////////////////        1442.                                                                            // MODULE: xbus.sub.-- cnt                                                 1443.                                                                            // a 2 and a 3 (3 was missing)                                             1444.                                                                            //                                                                         1445.                                                                            `define XBUS.sub.-- CNT.sub.-- REV 1.00                                    1446.                                                                            //                                                                         1447.                                                                            // PURPOSE: This block controls the XWRITE, XREAD, and IO16                1448.                                                                            // for the xbus based on controls comming from all blocks.                 1449.                                                                            //                                                                         1450.                                                                            module xbus.sub.-- cnt(CS.sub.-- IN, DLY.sub.-- SEL, DMAX,                    FORCE.sub.-- XRA, FORCE.sub.-- XW, FXDEC0, FXDEC2                          1451.                                                                            , IO16.sub.-- IN, IOR, IOW, REGCNT0, X0, X10, X11, X12, X13, X14, X15,        X1, X2                                                                     1452.                                                                            , X3, X4, X5, X6, X7, X8, X9, IO16, XREADA, XREADB, XWRITE);               1453.                                                                            input CS.sub.-- IN, FORCE.sub.-- XRA, FORCE.sub.-- XW, FXDEC0, FXDEC2,        IOR, IOW, REGCNT0;                                                         1454.                                                                            output IO16, XREADA, XREADB, XWRITE;                                       1455.                                                                            input [2:0] X9;                                                            1456.                                                                            input [2:0] X8;                                                            1457.                                                                            input [2:0] X7;                                                            1458.                                                                            input [2:0] X6;                                                            1459.                                                                            input [2:0] X5;                                                            1460.                                                                            input [2:0] X4;                                                            1461.                                                                            input [2:0] X3;                                                            1462.                                                                            input [2:0] X2;                                                            1463.                                                                            input [2:0] X1;                                                            1464.                                                                            input [2:0] X15;                                                           1465.                                                                            input [2:0] X14;                                                           1466.                                                                            input [2:0] X13;                                                           1467.                                                                            input [2:0] X12;                                                           1468.                                                                            input [2:0] X11;                                                           1469.                                                                            input [2:0] X10;                                                           1470.                                                                            input [2:0] X0;                                                            1471.                                                                            input [15:0] IO16.sub.-- IN;                                               1472.                                                                            input [1:0] DMAX;                                                          1473.                                                                            input [1:0] DLY.sub.-- SEL:                                                1474.                                                                            // These busses contain the control info [0]=XA.sub.-- SEL,                   [1]=XB.sub.-- SEL and                                                      1475.                                                                            // coming from the prog.sub.-- decode (X), DMA.sub.-- SW (DX), and            fix.sub.-- deco                                                            1476.                                                                            // (FXDEC) blocks                                                          1477.                                                                            wire CS.sub.-- XWH;                                                        1478.                                                                            wire IO16 = IO16.sub.-- IN[0] ∥ IO16.sub.-- IN[1] ∥         IO16.sub.-- IN[2] ∥ IO16.sub.-- IN[3] ∥ IO16.sub.--         IN[4] ∥ IO16.sub.-- IN[5] ∥                              1479.                                                                              IO16.sub.-- IN[6] ∥ IO16.sub.-- IN[7] ∥ IO16.sub.--        IN[8] ∥ IO16.sub.-- IN[9] ∥ IO16.sub.-- IN[10]             ∥ IO16.sub.-- IN[11] ∥                                   1480.                                                                              IO16.sub.-- IN[12] ∥ IO16.sub.-- IN[13] ∥ IO16.sub.       -- IN[14] ∥ IO16.sub.-- IN[15];                                   1481.                                                                            wire XA.sub.-- SEL = X0[0] ∥ X1[0] ∥ X2[0] ∥        X3[0] ∥ X4[0] ∥ X5[0] ∥                        1482.                                                                              X6[0] ∥ X7[0] ∥ X8[0] ∥ X9[0] ∥         X10[0] ∥                                                          1483.                                                                              X11[0] ∥ X12[0] ∥ X13[0] ∥ X14[0]                ∥ X15[0] ∥                                               1484.                                                                              DMAX[0] ∥ CS.sub.-- IN ∥ FXDEC0 ∥                REGCNT0;                                                                   1485.                                                                            wire XB.sub.-- SEL = X0[1] ∥ X1[1] ∥ X2[1] ∥        X3[1] ∥ X4[1] ∥ X5[1] ∥                        1486.                                                                              X6[1] ∥ X7[1] ∥ X8[1] ∥ X9[1] ∥         X10[1] ∥                                                          1487.                                                                              X11[1] ∥ X12[1] ∥ X13[1] ∥ X14[1]                ∥ X15[1] ∥                                               1485.                                                                              DMAX[1];                                                                 1489.                                                                            wire IGNORE.sub.-- RD = X0[2] ∥ X1[2] ∥ X2[2]               ∥ X3[2] ∥ X4[2] ∥ X5[2] ∥              1490.                                                                              X6[2] ∥ X7[2] ∥ X8[2] ∥ X9[2] ∥         X10[2] ∥                                                          1491.                                                                              X11[2] ∥ X12[2] ∥ X13[2] ∥ X14[2]                ∥ X15[2] ∥ FXDEC2;                                       1492.                                                                            wire DLY.sub.-- IOW; // programmable delayed version of IOW                1493.                                                                            prog.sub.-- dly UDLY (.Z(DLY.sub.-- IOW),.A(IOW),                          1494.                                                                              .SEL0(DLY.sub.-- SEL[0]),.SEL1(DLY.sub.-- SEL[1]));                      1495.                                                                            wire XWRITE = FORCE.sub.-- XW ∥                                   1496.                                                                              !IOR && ((XA.sub.-- SEL ∥ XB.sub.-- SEL) && (IOW ∥        DLY.sub.-- IOW));                                                          1497.                                                                            wire XREADA = FORCE.sub.-- XRA ∥ (IOR && XA.sub.-- SEL &&            !IGNORE.sub.-- RD);                                                        1498.                                                                            wire XREADB = IOR && XB.sub.-- SEL && !IGNORE.sub.-- RD;                   1499.                                                                            endmodule // xbus.sub.-- cnt                                               __________________________________________________________________________

What is claimed is:
 1. A method for establishing data transfer between asystem controller and one or more predetermined option cards, eachoption card having an option databus and one or more input/outputdevices, said devices having a programmably selectable addressesthereon, comprising the steps of:coupling address data and controlsignals from the computer system to said programmably selectableaddresses; providing data storage for storing said programmablyselectable addresses; comparing system addresses with said storedprogrammable selectable addresses to determine when said systemcontroller addresses said stored programmable selectable addresses;providing decoding of predetermined programmed commands and qualifiers;defining a user selectable mode of data transfer between the systemcontroller and the option card as either an address decode mode, anindex decode mode or a third mode, providing decoding of said userselectable mode of data transfer and automatically disabling thenonselected mode of data transfer; and selecting said one or moreinput/output devices responsive to said storing step providing addressdecoding of said programmable selectable addresses of said one or moreinput/output devices on said option card and said decoding step decodingpredetermined commands and qualifiers in accordance with the definedmode of transfer.
 2. A method in accordance with claim 1 furthercomprising the step of multiplexing data stored in the data storage bysaid storing step to the system controller allowing such data to be readthereby.
 3. A method in accordance wtih claim 1, wherein providing stepprovides a plurality of data storage devices connected to the systemcontroller.
 4. A method in accordance wtih claim 3, wherein saidplurality of storage devices provide address decoding of theinput/output device to define an index mode of operation for datatransfer between the system controller and the option card.
 5. A methodin accordance with claim 1 wherein data stored in said storing step isprovided from said providing step to define an address mode of operationto address the input/output device providing data transfer between thesystem controller and the option card.
 6. A method in accordance wtihclaim 1 wherein said selecting step further selects the input/outputdevice responsive to address signals obtained to the system controller.7. A method in accordance wtih claim 1, wherein said selecting stepfurther selects the input/output device responsive to control signalsobtained from the system controller.